On Tue, Sep 22, 2015 at 10:50:21AM +0100, Hou Zhiqiang wrote:
> Hi Mark,
>
> > -----Original Message-----
> > From: Mark Rutland [mailto:[email protected]]
> > Sent: 2015年9月22日 9:24
> > To: Hou Zhiqiang-B48286; [email protected]
> > Cc: [email protected]; Catalin Marinas; Will Deacon;
> > [email protected]; [email protected]; linux-
> > [email protected]; [email protected]; Xie Shaohui-B21989;
> > [email protected]; Sharma Bhupesh-B45370; [email protected]; wsa@the-
> > dreams.de; [email protected]; [email protected]; Song Wenbin-B53747; Wood
> > Scott-B07421; Hu Mingkai-B21284; Li Yang-Leo-R58472
> > Subject: Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
> >
> > Hi,
> >
> > > +/memreserve/ 0x80000000 0x00010000;
> >
> > Why is this necessary?
>
> This memory region is pre-reserved for the spin-table/psci, although didn't
> add
> Enable method of secondary cores.
Your PSCI implementation isn't in secure memory?
> > > + ifc: ifc@1530000 {
> > > + compatible = "fsl,ifc", "simple-bus";
> > > + reg = <0x0 0x1530000 0x0 0x10000>;
> > > + interrupts = <0 43 0x4>;
> > > + };
> >
> > Why simple-bus?
>
> There are 3 child node located in dtsi file that should be created and added
> to platform device list.
Are they usable even if the kernel knew nothing about the IFC node? If not, the
IFC driver should probe them, and simple-bus should go.
> > > + memory@80000000 {
> > > + device_type = "memory";
> > > + reg = <0x0 0x80000000 0 0x80000000>;
> > > + /* DRAM space 1 - 2 GB DRAM */
> >
> > I don't understand the comment. This describes 2GB at 2GB.
> >
>
> Yes, there is a 2GB space for DRAM from address 2G.
> The DRAM address 0x0 will be remapped to SoC address 2G, this remap is done
> by hardware.
I just realised my mistake -- I read this as "1 to 2 GB", when this is actually
"DRAM space 1". Sorry for the noise.
Thanks,
Mark.
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