From: Haim Dreyfuss <haim.dreyf...@intel.com>

CSR registers are always available even when the NIC is not awake, no
need to wake up the NIC before accessing them. This has a huge impact
when we re-enable an interrupt at the end of the ISR since waking up the
NIC can take some time.

Signed-off-by: Haim Dreyfuss <haim.dreyf...@intel.com>
Signed-off-by: Luca Coelho <luciano.coe...@intel.com>
---
 drivers/net/wireless/intel/iwlwifi/pcie/rx.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/rx.c 
b/drivers/net/wireless/intel/iwlwifi/pcie/rx.c
index 7f8a232..89f87f7 100644
--- a/drivers/net/wireless/intel/iwlwifi/pcie/rx.c
+++ b/drivers/net/wireless/intel/iwlwifi/pcie/rx.c
@@ -1298,7 +1298,7 @@ static inline void iwl_pcie_clear_irq(struct iwl_trans 
*trans,
         * write 1 clear (W1C) register, meaning that it's being clear
         * by writing 1 to the bit.
         */
-       iwl_write_direct32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry));
+       iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry));
 }
 
 /*
@@ -1817,13 +1817,13 @@ irqreturn_t iwl_pcie_irq_msix_handler(int irq, void 
*dev_id)
        lock_map_acquire(&trans->sync_cmd_lockdep_map);
 
        spin_lock(&trans_pcie->irq_lock);
-       inta_fh = iwl_read_direct32(trans, CSR_MSIX_FH_INT_CAUSES_AD);
-       inta_hw = iwl_read_direct32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
+       inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD);
+       inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
        /*
         * Clear causes registers to avoid being handling the same cause.
         */
-       iwl_write_direct32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh);
-       iwl_write_direct32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);
+       iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh);
+       iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);
        spin_unlock(&trans_pcie->irq_lock);
 
        if (unlikely(!(inta_fh | inta_hw))) {
-- 
2.8.1

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