From: Quanyang Wang <[email protected]>
When assigning value to a pointer as below:
itapdly = (u32 [MMC_TIMING_MMC_HS400 + 1]) {0x0, 0x15, 0x15...0x0};
then using gcc 9.2.0 with -O2 to compile, the pointer itapdly will point to
the stack of the function, and the values in this area is not initialized.
The disassemble code is as below:
ffffffc010a389b8: 940089ac bl ffffffc010a5b068
<of_device_is_compatible>
ffffffc010a389bc: 34001100 cbz w0, ffffffc010a38bdc
<arasan_dt_parse_tap_delays+0x264>
itapdly = (u32 [MMC_TIMING_MMC_HS400 + 1]) ZYNQMP_ITAP_DELAYS;
otapdly = (u32 [MMC_TIMING_MMC_HS400 + 1]) ZYNQMP_OTAP_DELAYS;
ffffffc010a389c0: 9101d3f4 add x20, sp, #0x74
itapdly = (u32 [MMC_TIMING_MMC_HS400 + 1]) ZYNQMP_ITAP_DELAYS;
ffffffc010a389c4: 910123f5 add x21, sp, #0x48
int ret = of_property_read_variable_u32_array(np, propname,
out_values,
This results that the pointer itapdly is not the address of the array
ZYNQMP_ITAP_DELAYS but a stack address which contains random values.
So use an array of integers to avoid the over optimization of the new
compiler.
Signed-off-by: Quanyang Wang <[email protected]>
--
drivers/mmc/host/sdhci-of-arasan.c | 25 +++++++++++++------------
1 file changed, 13 insertions(+), 12 deletions(-)
---
drivers/mmc/host/sdhci-of-arasan.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/mmc/host/sdhci-of-arasan.c
index bc9ca6ae20ce..34dcded79b78 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -52,15 +52,15 @@
#define SDHCI_ITAPDLY_ENABLE 0x100
#define SDHCI_OTAPDLY_ENABLE 0x40
-#define ZYNQMP_ITAP_DELAYS {0x0, 0x15, 0x15, 0x0, 0x15, 0x0,\
- 0x0, 0x3D, 0x12, 0x0, 0x0}
-#define ZYNQMP_OTAP_DELAYS {0x0, 0x5, 0x6, 0x0, 0x5, 0x3,\
- 0x3, 0x4, 0x6, 0x3, 0x0}
+static u32 zynqmp_itap_delays[MMC_TIMING_MMC_HS400+1] = {0x0, 0x15, 0x15, 0x0,
+ 0x15, 0x0, 0x0, 0x3D, 0x12, 0x0, 0x0};
+static u32 zynqmp_otap_delays[MMC_TIMING_MMC_HS400+1] = {0x0, 0x5, 0x6, 0x0,
+ 0x5, 0x3, 0x3, 0x4, 0x6, 0x3, 0x0};
-#define VERSAL_ITAP_DELAYS {0x0, 0x2C, 0x2C, 0x0, 0x2C, 0x0,\
- 0x0, 0x36, 0x1E, 0x0, 0x0}
-#define VERSAL_OTAP_DELAYS {0x0, 0x5, 0x4, 0x0, 0x4, 0x3,\
- 0x2, 0x3, 0x5, 0x2, 0x0}
+static u32 versal_itap_delays[MMC_TIMING_MMC_HS400 + 1] = {0x0, 0x2C, 0x2C,
+ 0x0, 0x2C, 0x0, 0x0, 0x36, 0x1E, 0x0, 0x0};
+static u32 versal_otap_delays[MMC_TIMING_MMC_HS400 + 1] = {0x0, 0x5, 0x4,
+ 0x0, 0x4, 0x3, 0x2, 0x3, 0x5, 0x2, 0x0};
#define MMC_BANK2 0x2
@@ -995,15 +995,15 @@ static void arasan_dt_parse_tap_delays(struct device *dev)
int i;
if (of_device_is_compatible(pdev->dev.of_node, "xlnx,zynqmp-8.9a")) {
- itapdly = (u32 [MMC_TIMING_MMC_HS400 + 1]) ZYNQMP_ITAP_DELAYS;
- otapdly = (u32 [MMC_TIMING_MMC_HS400 + 1]) ZYNQMP_OTAP_DELAYS;
+ itapdly = zynqmp_itap_delays;
+ otapdly = zynqmp_otap_delays;
if (sdhci_arasan->mio_bank == MMC_BANK2) {
otapdly[MMC_TIMING_UHS_SDR104] = 0x2;
otapdly[MMC_TIMING_MMC_HS200] = 0x2;
}
} else {
- itapdly = (u32 [MMC_TIMING_MMC_HS400 + 1]) VERSAL_ITAP_DELAYS;
- otapdly = (u32 [MMC_TIMING_MMC_HS400 + 1]) VERSAL_OTAP_DELAYS;
+ itapdly = versal_itap_delays;
+ otapdly = versal_otap_delays;
}
arasan_dt_read_tap_delay(dev, itapdly, MMC_TIMING_SD_HS,
--
2.17.1
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