The TI AM65x SoCs Gigabit Ethernet Switch subsystem (CPSW2G NUSS) has two ports - One Ethernet port (port 1) with selectable RGMII and RMII interfaces and an internal Communications Port Programming Interface (CPPI) port (Host port 0) and with ALE in between. It also contains - Management Data Input/Output (MDIO) interface for physical layer device (PHY) management; - Updated Address Lookup Engine (ALE) module; - (TBD) New version of Common platform time sync (CPTS) module;
Signed-off-by: Jun Miao <[email protected]> --- bsp/ti-am65x/ti-am65x.cfg | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/bsp/ti-am65x/ti-am65x.cfg b/bsp/ti-am65x/ti-am65x.cfg index 008d388b..4d628d36 100644 --- a/bsp/ti-am65x/ti-am65x.cfg +++ b/bsp/ti-am65x/ti-am65x.cfg @@ -158,6 +158,8 @@ CONFIG_SPI_CADENCE_QUADSPI=y CONFIG_DMADEVICES=y CONFIG_DMA_ENGINE=y CONFIG_DMA_OF=y +CONFIG_TI_K3_UDMA=y +CONFIG_TI_K3_UDMA_GLUE_LAYER=y # # Common Clock Framework @@ -165,6 +167,7 @@ CONFIG_DMA_OF=y CONFIG_TI_SCI_CLK=y CONFIG_TI_SCI_PROTOCOL=y CONFIG_TI_SCI_CLK_PROBE_FROM_FW=y +CONFIG_PTP_1588_CLOCK=y # # Qualcomm SoC drivers @@ -194,3 +197,11 @@ CONFIG_PHY_AM654_SERDES=y CONFIG_PHYLIB=y CONFIG_NETDEVICES=y CONFIG_DP83867_PHY=y + +# +# NET Support +# +CONFIG_TI_K3_RINGACC=y +CONFIG_TI_K3_AM65_CPSW_NUSS=y +CONFIG_TI_CPSW_PHY_SEL=y +CONFIG_TI_K3_AM65_CPTS=y -- 2.22.0
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