Hi Amit,

On 4/7/22 19:40, Amit Kumar Mahapatra wrote:
Hello Quanyang,

-----Original Message-----
From: Quanyang Wang <[email protected]>
Sent: Friday, March 11, 2022 5:20 PM
To: Amit Kumar Kumar Mahapatra <[email protected]>; Bruce
<[email protected]>; Michal Simek <[email protected]>
Cc: [email protected]
Subject: Re: [PATCH 6/7] Revert "mtd: spi-nor: Set proper block protection
bits for Winbond flashes"

Hi Amit,

On 3/11/22 19:31, Amit Kumar Kumar Mahapatra wrote:
Hello Quanyang,

-----Original Message-----
From: [email protected]
<[email protected]>
Sent: Tuesday, October 19, 2021 1:46 PM
To: Bruce <[email protected]>; [email protected]
Cc: [email protected];
[email protected]
Subject: [PATCH 6/7] Revert "mtd: spi-nor: Set proper block
protection bits for Winbond flashes"

From: Quanyang Wang <[email protected]>

This reverts commit d2944ea38702eb5b3efcbd36bffcb35dffd7fe15.

Now the code for flash lock/unlock in linux-yocto can work with
zynqmp/zc706/zc702 boards and the SDK patches break them. let's revert
it.
Reverting this patch might result in flash lock/unlock failure on Winbond
flash parts.
can you please confirm that Winbond flash part is tested with this patch
series ?

I only have zcu102/zc706/zc702, they don't have Winbond flash.

So this patch series just work for the flashes at zcu102 and zcu702 boards.
By default we have Micron flashes on both zcu102 and zc702 boards.
But the patches that you are reverting in this series would affect all qspi 
flashes.
With this patch series we are observing flash lock/unlock failure with Winbond 
& Spansion
Flash parts. Due to this failures we cannot push this patch series, in its 
current form, to our tree.
I understand. Please ignore this patch.

Thanks,

Quanyang


Regards,
Amit
Thanks,

Quanyang

Regards,
Amit
Signed-off-by: Quanyang Wang <[email protected]>
---
   drivers/mtd/spi-nor/core.c    | 21 ---------------------
   drivers/mtd/spi-nor/core.h    |  6 +-----
   drivers/mtd/spi-nor/winbond.c |  5 +----
   include/linux/mtd/spi-nor.h   |  1 -
   4 files changed, 2 insertions(+), 31 deletions(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index
61dd5785d2f55..c9dcd9ce66da2 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -1672,8 +1672,6 @@ static u8 spi_nor_get_sr_bp_mask(struct
spi_nor
*nor)

        if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6)
                return mask | SR_BP3_BIT6;
-       else if (nor->flags & SNOR_F_HAS_SR_BP3_BIT5)
-               return mask | SR_BP3_BIT5;

        if (nor->flags & SNOR_F_HAS_4BIT_BP)
                return mask | SR_BP3;
@@ -1878,9 +1876,6 @@ static int spi_nor_sr_lock(struct spi_nor *nor,
loff_t ofs, uint64_t len)

                if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3)
                        val = (val & ~SR_BP3) | SR_BP3_BIT6;
-               else if (nor->flags & SNOR_F_HAS_SR_BP3_BIT5 &&
-                        val & SR_BP3_BIT5)
-                       val |= SR_BP3_BIT5;

                if (val & ~mask)
                        return -EINVAL;
@@ -1967,9 +1962,6 @@ static int spi_nor_sr_unlock(struct spi_nor
*nor, loff_t ofs, uint64_t len)

                if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3)
                        val = (val & ~SR_BP3) | SR_BP3_BIT6;
-               else if (nor->flags & SNOR_F_HAS_SR_BP3_BIT5 &&
-                        val & SR_BP3_BIT5)
-                       val |= SR_BP3_BIT5;

                /* Some power-of-two sizes are not supported */
                if (val & ~mask)
@@ -2038,14 +2030,6 @@ static int write_sr_modify_protection(struct
spi_nor *nor, u8 status,

                if (lock_bits > 7)
                        bp_mask |= SR_BP3;
-       } else if (nor->jedec_id == CFI_MFR_WINBND) { /* Winbond */
-               status_new &= ~SR_BP3_BIT5;
-
-               /* Protected area starts from top */
-               status_new &= ~SR_BP_TB;
-
-               if (lock_bits > 7)
-                       bp_mask |= SR_BP3_BIT5;
        }

        if (nor->is_lock)
@@ -2072,9 +2056,6 @@ static u8 bp_bits_from_sr(struct spi_nor *nor,
u8
status)
        ret = (((status) & SR_BP_BIT_MASK) >> SR_BP_BIT_OFFSET);
        if (nor->jedec_id == 0x20)
                ret |= ((status & SR_BP3) >> (SR_BP_BIT_OFFSET + 1));
-       else if ((nor->jedec_id == CFI_MFR_WINBND) &&
-                (nor->flags & SNOR_F_HAS_4BIT_BP))
-               ret |= ((status & SR_BP3_BIT5) >> SR_BP_BIT_OFFSET);

        return ret;
   }
@@ -3976,8 +3957,6 @@ int spi_nor_scan(struct spi_nor *nor, const
char *name,
                nor->flags |= SNOR_F_HAS_4BIT_BP;
                if (info->flags & SPI_NOR_BP3_SR_BIT6)
                        nor->flags |= SNOR_F_HAS_SR_BP3_BIT6;
-               else if (info->flags & SPI_NOR_BP3_SR_BIT5)
-                       nor->flags |= SNOR_F_HAS_SR_BP3_BIT5;
        }

        if (info->flags & SPI_NOR_NO_ERASE) diff --git
a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index
9165b06f1ebef..7fcabb55c6f88 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -26,7 +26,6 @@ enum spi_nor_option_flags {
        SNOR_F_HAS_SR_TB_BIT6   = BIT(11),
        SNOR_F_HAS_4BIT_BP      = BIT(12),
        SNOR_F_HAS_SR_BP3_BIT6  = BIT(13),
-       SNOR_F_HAS_SR_BP3_BIT5  = BIT(14),
   };

   struct spi_nor_read_command {
@@ -316,10 +315,7 @@ struct flash_info {
   #define      SST_GLOBAL_PROT_UNLK    BIT(16) /* Unlock the Global
protection for
                                         * sst flashes
                                         */
-#define SPI_NOR_BP3_SR_BIT5    BIT(20) /*
-                                        * BP3 is bit 5 of status register.
-                                        * Must be used with
SPI_NOR_4BIT_BP.
-                                        */
+
        int     (*quad_enable)(struct spi_nor *nor);
        /* Part specific fixup hooks. */
        const struct spi_nor_fixups *fixups; diff --git
a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index
ed4f4ff91e74c..f55cd26383962 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -98,10 +98,7 @@ static struct flash_info winbond_parts[] = {
        { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
                            SECT_4K | SPI_NOR_QUAD_READ |
SPI_NOR_DUAL_READ) },
        { "w25h02jv", INFO(0xef9022, 0, 64 * 1024, 4096,
-                           SECT_4K | SPI_NOR_QUAD_READ |
SPI_NOR_DUAL_READ |
-                           SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
-                           SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP |
-                           SPI_NOR_BP3_SR_BIT5) },
+                           SECT_4K | SPI_NOR_QUAD_READ |
SPI_NOR_DUAL_READ) },
   };

   /**
diff --git a/include/linux/mtd/spi-nor.h
b/include/linux/mtd/spi-nor.h index
ff9aa6df0ab81..5d5eee3f2d780 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -128,7 +128,6 @@
   #define SR_BP3                 BIT(6)  /* Block protect 3 */
   #define SR_TB_BIT5           BIT(5)  /* Top/Bottom protect */
   #define SR_BP3_BIT6          BIT(6)  /* Block protect 3 */
-#define SR_BP3_BIT5            BIT(5)  /* Block protect 3 */
   #define SR_TB_BIT6           BIT(6)  /* Top/Bottom protect */
   #define SR_SRWD                      BIT(7)  /* SR write protect */
   /* Bit to determine whether protection starts from top or bottom */
--
2.25.1
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