merged.

Bruce

In message: [linux-yocto][linux-yocto v5.15/standard/nxp-sdk-5.15/nxp-soc & 
v5.15/standard/preempt-rt/nxp-sdk-5.15/nxp-soc][PATCH] ARM64: dts: imx8mq: Fix 
a build error Unable to parse input tree
on 19/05/2022 Xiaolei Wang wrote:

> Due to the porting error of commit 38dad434a6b7("ARM64:
> dts: imx8mq: add csi and mipi csi node"), the property
> that needs to be deleted is not deleted.
> 
> Signed-off-by: Xiaolei Wang <[email protected]>
> ---
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi | 22 +++-------------------
>  1 file changed, 3 insertions(+), 19 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi 
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 6d6d2fe9b9b0..60cb0625114d 100755
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -1159,33 +1159,17 @@ mipi_csi_1: mipi_csi1@30a70000 {
>                               reg = <0x30a70000 0x1000>;
>                               interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
>                               clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
> -                                <&clk IMX8MQ_CLK_CSI1_ESC>,
> -                                <&clk IMX8MQ_CLK_CSI1_PHY_REF>;
> -                             clock-names = "core", "esc", "ui";
>                                               <&clk IMX8MQ_CLK_CSI1_ESC>,
>                                               <&clk IMX8MQ_CLK_CSI1_PHY_REF>;
>                               clock-names = "clk_core", "clk_esc", "clk_pxl";
>                               assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
> -                                 <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
> -                                 <&clk IMX8MQ_CLK_CSI1_ESC>;
> -                             assigned-clock-rates = <266000000>, 
> <333000000>, <66000000>;
> -                             assigned-clock-parents = <&clk 
> IMX8MQ_SYS1_PLL_266M>,
> -                                     <&clk IMX8MQ_SYS2_PLL_1000M>,
> -                                     <&clk IMX8MQ_SYS1_PLL_800M>;
> -                                             <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
> -                                             <&clk IMX8MQ_CLK_CSI1_ESC>;
> -                             assigned-clock-rates = <133000000>, 
> <100000000>, <66000000>;
> +                                               <&clk 
> IMX8MQ_CLK_CSI1_PHY_REF>,
> +                                               <&clk IMX8MQ_CLK_CSI1_ESC>;
> +                                               assigned-clock-rates = 
> <133000000>, <100000000>, <66000000>;
>                               power-domains = <&pgc_mipi_csi1>;
> -                             resets = <&src 
> IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>,
> -                                      <&src 
> IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>,
> -                                      <&src 
> IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>;
> -                             fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
> -                             interconnects = <&noc IMX8MQ_ICM_CSI1 &noc 
> IMX8MQ_ICS_DRAM>;
> -                             interconnect-names = "dram";
>                               csis-phy-reset = <&src 0x4c 7>;
>                               phy-gpr = <&iomuxc_gpr 0x88>;
>                               status = "disabled";
> -
>                       };
>  
>                       csi1_bridge: csi1_bridge@30a90000 {
> -- 
> 2.25.1
> 
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