We have observed the following call trace on the i.MX8QM MEK board. In theory, the power domain IMX_SC_R_MIPI_0_I2C_X should be a subdomain of IMX_SC_R_MIPI_X. But the power domain is maintained by the System Controller Firmware and it seems that the IMX_SC_R_MIPI_X power domain could be powered off even the IMX_SC_R_MIPI_0_I2C_X is active. This seems to be an issue in the firmware. Adjust the power domain of the mipix_i2cx_lpcg* clocks to IMX_SC_R_MIPI_X to workaourn this issue.
SError Interrupt on CPU4, code 0xbf000002 -- SError CPU: 4 PID: 5269 Comm: rtcwake Tainted: G W 5.15.37-yocto-standard #1 Hardware name: Freescale i.MX8QM MEK (DT) pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : genpd_lock_mtx+0x10/0x30 lr : genpd_finish_suspend+0x110/0x1bc sp : ffff80000ff5ba10 x29: ffff80000ff5ba10 x28: ffff800008b53674 x27: ffff80000b0e6608 x26: 0000000000000002 x25: ffff80000a0e9d0c x24: ffff80000b011658 x23: 0000000000000000 x22: ffff00081321b608 x21: 0000000000000000 x20: ffff000812049810 x19: ffff00081321b080 x18: ffffffffffffffff x17: 207369202977683e x16: 2d6b6c632628656d x15: 616e5f7465675f77 x14: 0000000000000000 x13: 0d0a206b6c635f67 x12: 70695f6763706c5f x11: 000000000004800d x10: ffff80000a0ea8e0 x9 : ffff800008b5c2d4 x8 : 00000000fffdffff x7 : ffff80000abea8e0 x6 : 0000000000000001 x5 : ffff80000a0c1000 x4 : ffff80000a0c1568 x3 : 0000000000000000 x2 : 0000000000000000 x1 : ffff800008b58100 x0 : ffff00081321b080 Kernel panic - not syncing: Asynchronous SError Interrupt CPU: 4 PID: 5269 Comm: rtcwake Tainted: G W 5.15.37-yocto-standard #1 Hardware name: Freescale i.MX8QM MEK (DT) Call trace: dump_backtrace+0x0/0x1b0 show_stack+0x24/0x30 dump_stack_lvl+0xb0/0xf4 dump_stack+0x18/0x34 panic+0x184/0x37c add_taint+0x0/0xc0 arm64_serror_panic+0x70/0x80 is_valid_bugaddr+0x0/0x2c el1h_64_error_handler+0x38/0x50 el1h_64_error+0x78/0x7c genpd_lock_mtx+0x10/0x30 genpd_suspend_noirq+0x20/0x30 dpm_run_callback+0x40/0x90 __device_suspend_noirq+0xec/0x244 dpm_noirq_suspend_devices+0x13c/0x220 dpm_suspend_noirq+0x34/0xb0 suspend_devices_and_enter+0x26c/0x54c pm_suspend+0x2b0/0x340 state_store+0x98/0x11c kobj_attr_store+0x1c/0x30 sysfs_kf_write+0x58/0x84 kernfs_fop_write_iter+0x12c/0x1c0 new_sync_write+0x108/0x1a4 vfs_write+0x1c8/0x21c ksys_write+0x78/0x104 __arm64_sys_write+0x28/0x3c invoke_syscall+0x5c/0x130 el0_svc_common.constprop.0+0x68/0x124 do_el0_svc+0x50/0xbc el0_svc+0x54/0x130 el0t_64_sync_handler+0xa4/0x130 el0t_64_sync+0x1a0/0x1a4 SMP: stopping secondary CPUs Kernel Offset: disabled CPU features: 0x200020b1,20000842 Memory Limit: none Signed-off-by: Xiaolei Wang <[email protected]> --- .../arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi index ba166abbab3c..fa6f0ffc8c42 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi @@ -52,7 +52,7 @@ mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 { clocks = <&dsi_ipg_clk>; bit-offset = <0>; clock-output-names = "mipi0_i2c0_lpcg_ipg_s_clk"; - power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + power-domains = <&pd IMX_SC_R_MIPI_0>; }; mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 { @@ -62,7 +62,7 @@ mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 { clocks = <&mipi0_i2c0_lpcg_ipg_s_clk 0>; bit-offset = <0>; clock-output-names = "mipi0_i2c0_lpcg_ipg_clk"; - power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + power-domains = <&pd IMX_SC_R_MIPI_0>; }; mipi0_i2c1_lpcg_clk: clock-controller@5622302c { @@ -82,7 +82,7 @@ mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 { clocks = <&dsi_ipg_clk>; bit-offset = <0>; clock-output-names = "mipi0_i2c1_lpcg_ipg_s_clk"; - power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>; + power-domains = <&pd IMX_SC_R_MIPI_0>; }; mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 { @@ -92,7 +92,7 @@ mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 { clocks = <&mipi0_i2c1_lpcg_ipg_s_clk 0>; bit-offset = <0>; clock-output-names = "mipi0_i2c1_lpcg_ipg_clk"; - power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>; + power-domains = <&pd IMX_SC_R_MIPI_0>; }; irqsteer_mipi0: irqsteer@56220000 { @@ -217,7 +217,7 @@ mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 { clocks = <&dsi_ipg_clk>; bit-offset = <0>; clock-output-names = "mipi1_i2c0_lpcg_ipg_s_clk"; - power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + power-domains = <&pd IMX_SC_R_MIPI_1>; }; mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 { @@ -227,7 +227,7 @@ mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 { clocks = <&mipi1_i2c0_lpcg_ipg_s_clk 0>; bit-offset = <0>; clock-output-names = "mipi1_i2c0_lpcg_ipg_clk"; - power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + power-domains = <&pd IMX_SC_R_MIPI_1>; }; mipi1_i2c1_lpcg_clk: clock-controller@5722302c { @@ -247,7 +247,7 @@ mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 { clocks = <&dsi_ipg_clk>; bit-offset = <0>; clock-output-names = "mipi1_i2c1_lpcg_ipg_s_clk"; - power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>; + power-domains = <&pd IMX_SC_R_MIPI_1>; }; mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 { @@ -257,7 +257,7 @@ mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 { clocks = <&mipi1_i2c1_lpcg_ipg_s_clk 0>; bit-offset = <0>; clock-output-names = "mipi1_i2c1_lpcg_ipg_clk"; - power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>; + power-domains = <&pd IMX_SC_R_MIPI_1>; }; irqsteer_mipi1: irqsteer@57220000 { -- 2.25.1
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