In message: [linux-yocto PATCH] Revert "octeontx2-af: Unlock contexts in the queue context cache in case of fault detection" on 19/03/2023 Kevin Hao wrote:
> From: Kevin Hao <[email protected]> > > Revert the changes introduced by the stable commit 64d4eb412761 > ("octeontx2-af: Unlock contexts in the queue context cache in case of > fault detection") since there was already a SDK commit 23752817e9eb > ("octeontx2-af: Unlock NDCX_AF_BANKX_LINEX_METADATA during NDC > fault/lockerror/poison.") to fix the same issue. > > Signed-off-by: Kevin Hao <[email protected]> > --- > Hi Bruce, > > Please help me merge this patch into the following two branches: > v5.15/standard/cn-sdkv5.4/octeon > v5.15/standard/preempt-rt/cn-sdkv5.4/octeon merged. Bruce > > .../net/ethernet/marvell/octeontx2/af/rvu.h | 5 -- > .../marvell/octeontx2/af/rvu_debugfs.c | 4 +- > .../ethernet/marvell/octeontx2/af/rvu_npa.c | 47 +------------------ > 3 files changed, 2 insertions(+), 54 deletions(-) > > diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h > b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h > index 93e22a2ef647..3e5d618bea38 100644 > --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h > +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h > @@ -1091,9 +1091,6 @@ u32 rvu_get_cpt_chan_mask(struct rvu *rvu); > #define NDC_MAX_LINE_PER_BANK(rvu, blk_addr) ((rvu_read64(rvu, \ > blk_addr, NDC_AF_CONST) & 0xFFFF0000) > >> 16) > > -#define NDC_AF_BANK_MASK GENMASK_ULL(7, 0) > -#define NDC_AF_BANK_LINE_MASK GENMASK_ULL(31, 16) > - > /* CN10K RVU */ > int rvu_set_channels_base(struct rvu *rvu); > void rvu_program_channels(struct rvu *rvu); > @@ -1129,8 +1126,6 @@ static inline void rvu_dbg_init(struct rvu *rvu) {} > static inline void rvu_dbg_exit(struct rvu *rvu) {} > #endif > > -int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr); > - > /* RVU Switch */ > void rvu_switch_enable(struct rvu *rvu); > void rvu_switch_disable(struct rvu *rvu); > diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c > b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c > index 0ef62d35d81e..58f9bb055c53 100644 > --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c > +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c > @@ -1446,7 +1446,6 @@ static int ndc_blk_hits_miss_stats(struct seq_file *s, > int idx, int blk_addr) > struct nix_hw *nix_hw; > struct rvu *rvu; > int bank, max_bank; > - u64 ndc_af_const; > > if (blk_addr == BLKADDR_NDC_NPA0) { > rvu = s->private; > @@ -1455,8 +1454,7 @@ static int ndc_blk_hits_miss_stats(struct seq_file *s, > int idx, int blk_addr) > rvu = nix_hw->rvu; > } > > - ndc_af_const = rvu_read64(rvu, blk_addr, NDC_AF_CONST); > - max_bank = FIELD_GET(NDC_AF_BANK_MASK, ndc_af_const); > + max_bank = NDC_MAX_BANK(rvu, blk_addr); > for (bank = 0; bank < max_bank; bank++) { > seq_printf(s, "BANK:%d\n", bank); > seq_printf(s, "\tHits:\t%lld\n", > diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c > b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c > index 3256a928ee36..339130a91cc2 100644 > --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c > +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c > @@ -4,7 +4,7 @@ > * Copyright (C) 2018 Marvell. > * > */ > -#include <linux/bitfield.h> > + > #include <linux/module.h> > #include <linux/pci.h> > > @@ -555,48 +555,3 @@ void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, > int npalf) > > npa_ctx_free(rvu, pfvf); > } > - > -/* Due to an Hardware errata, in some corner cases, AQ context lock > - * operations can result in a NDC way getting into an illegal state > - * of not valid but locked. > - * > - * This API solves the problem by clearing the lock bit of the NDC block. > - * The operation needs to be done for each line of all the NDC banks. > - */ > -int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr) > -{ > - int bank, max_bank, line, max_line, err; > - u64 reg, ndc_af_const; > - > - /* Set the ENABLE bit(63) to '0' */ > - reg = rvu_read64(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL); > - rvu_write64(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL, reg & > GENMASK_ULL(62, 0)); > - > - /* Poll until the BUSY bits(47:32) are set to '0' */ > - err = rvu_poll_reg(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL, > GENMASK_ULL(47, 32), true); > - if (err) { > - dev_err(rvu->dev, "Timed out while polling for NDC CAM busy > bits.\n"); > - return err; > - } > - > - ndc_af_const = rvu_read64(rvu, blkaddr, NDC_AF_CONST); > - max_bank = FIELD_GET(NDC_AF_BANK_MASK, ndc_af_const); > - max_line = FIELD_GET(NDC_AF_BANK_LINE_MASK, ndc_af_const); > - for (bank = 0; bank < max_bank; bank++) { > - for (line = 0; line < max_line; line++) { > - /* Check if 'cache line valid bit(63)' is not set > - * but 'cache line lock bit(60)' is set and on > - * success, reset the lock bit(60). > - */ > - reg = rvu_read64(rvu, blkaddr, > - NDC_AF_BANKX_LINEX_METADATA(bank, > line)); > - if (!(reg & BIT_ULL(63)) && (reg & BIT_ULL(60))) { > - rvu_write64(rvu, blkaddr, > - NDC_AF_BANKX_LINEX_METADATA(bank, > line), > - reg & ~BIT_ULL(60)); > - } > - } > - } > - > - return 0; > -} > -- > 2.39.2 >
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