From: Bogdan Roman <[email protected]> commit 9133b22fcbe14598c74fbd233482450e01834483 from https://github.com/nxp-auto-linux/linux
The MX25UW51245G flash memory on s32r45-evb and s32gxxxaevb boards fit in the 'Q' automotive grade (MX25UW51245GXDQ00), as opposed to the other platforms which have an 'R' automotive grade memory (MX25UW51245GXDR00). Among others, a difference for these types is the maximmum supported frequency: MX25UW51245GXDQ00 - 166 MHz MX25UW51245GXDR00 - 200 MHz Up until now, the s32gxxxaevb platforms were wrongly configured with the 200 MHz frequency. For the MX25UW51245GXDQ00 memory, the maximum supported frequency is 166 MHz. However, getting this frequency would require further modifications in the clock tree configuration. For now, set the frequency to 133 MHz as a conservative approach, since this frequency can be obtained with the current clock configurations. Issue: ALB-9840 Signed-off-by: Bogdan Roman <[email protected]> Signed-off-by: Zhantao Tang <[email protected]> --- arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi index aad99bebe5de..d6c2463bc424 100644 --- a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi @@ -872,6 +872,10 @@ &pcie1 { &qspi { status = "okay"; + + mx25uw51245g@0 { + spi-max-frequency = <133333333>; + }; }; &llce_dte_sram { -- 2.25.1
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