From: Jiasheng Jiang <[email protected]>
[ Upstream commit 947c70a213769f60e9d5aca2bc88b50a1cfaf5a6 ]
Add check for dma_set_mask() and return the error if it fails.
Fixes: 1a6f854f7daa ("spi: cadence-quadspi: Add Xilinx Versal external DMA
support")
Signed-off-by: Jiasheng Jiang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Signed-off-by: Sasha Levin <[email protected]>
Signed-off-by: Kevin Hao <[email protected]>
---
Hi Bruce,
Please help me merge this patch onto the following two branches:
v6.1/standard/preempt-rt/sdkv6.1/xlnx-soc
v6.1/standard/sdkv6.1/xlnx-soc
The commit 485792480660 was introduced in the v6.1.35 stable kernel,
but the changes of that were overrode due to the merge conflict in the
above two branches. This tries to reapply that commit on these two
branches.
drivers/spi/spi-cadence-quadspi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-cadence-quadspi.c
b/drivers/spi/spi-cadence-quadspi.c
index 82a253eb6e6e..7eb6a0899d13 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -2170,7 +2170,9 @@ static int cqspi_probe(struct platform_device *pdev)
if (of_device_is_compatible(pdev->dev.of_node,
"xlnx,versal-ospi-1.0")) {
- dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
+ ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
+ if (ret)
+ goto probe_reset_failed;
if (cqspi->master_ref_clk_hz >= TAP_GRAN_SEL_MIN_FREQ)
writel(0x1, cqspi->iobase +
CQSPI_REG_VERSAL_ECO);
}
--
2.39.2
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