CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W
5.15.78-rt48-yocto-preempt-rt #1
Hardware name: Freescale i.MX7 Dual (Device Tree)
[<80110f4c>] (unwind_backtrace) from [<8010aef8>] (show_stack+0x18/0x1c)
[<8010aef8>] (show_stack) from [<80be4998>] (dump_stack_lvl+0x40/0x4c)
[<80be4998>] (dump_stack_lvl) from [<8015297c>] (__might_resched+0x16c/0x1f0)
[<8015297c>] (__might_resched) from [<80bf2d8c>] (rt_spin_lock+0x34/0x80)
[<80bf2d8c>] (rt_spin_lock) from [<8011e350>] (imx_set_cpu_jump+0x20/0x70)
[<8011e350>] (imx_set_cpu_jump) from [<8011bd64>]
(imx7d_enter_low_power_idle+0x2e4/0x30c)
[<8011bd64>] (imx7d_enter_low_power_idle) from [<80897bb8>]
(cpuidle_enter_state+0xe8/0x2f0)
[<80897bb8>] (cpuidle_enter_state) from [<80897e18>] (cpuidle_enter+0x3c/0x50)
[<80897e18>] (cpuidle_enter) from [<8015a748>] (do_idle+0x234/0x264)
[<8015a748>] (do_idle) from [<8015aa88>] (cpu_startup_entry+0x20/0x28)
[<8015aa88>] (cpu_startup_entry) from [<81001138>] (start_kernel+0x5b8/0x69c)
[<81001138>] (start_kernel) from [<00000000>] (0x0)
Signed-off-by: Xiaolei Wang <xiaolei.w...@windriver.com>
Signed-off-by: Bruce Ashfield <bruce.ashfi...@gmail.com>
---
arch/arm/mach-imx/src.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index 2a2fc431d5e7..affaa0428315 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -35,7 +35,7 @@
#define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
static void __iomem *src_base;
-static DEFINE_SPINLOCK(src_lock);
+static DEFINE_RAW_SPINLOCK(src_lock);
static bool m4_is_enabled;
static const int sw_reset_bits[5] = {
@@ -64,11 +64,11 @@ static int imx_src_reset_module(struct reset_controller_dev
*rcdev,
bit = 1 << sw_reset_bits[sw_reset_idx];
- spin_lock_irqsave(&src_lock, flags);
+ raw_spin_lock_irqsave(&src_lock, flags);
val = readl_relaxed(src_base + SRC_SCR);
val |= bit;
writel_relaxed(val, src_base + SRC_SCR);
- spin_unlock_irqrestore(&src_lock, flags);
+ raw_spin_unlock_irqrestore(&src_lock, flags);
timeout = jiffies + msecs_to_jiffies(1000);
while (readl(src_base + SRC_SCR) & bit) {
@@ -89,7 +89,7 @@ void imx_enable_cpu(int cpu, bool enable)
u32 mask, val;
cpu = cpu_logical_map(cpu);
- spin_lock(&src_lock);
+ raw_spin_lock(&src_lock);
if (cpu_is_imx7d()) {
/* enable core */
if (enable)
@@ -106,12 +106,12 @@ void imx_enable_cpu(int cpu, bool enable)
val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1);
writel_relaxed(val, src_base + SRC_SCR);
}
- spin_unlock(&src_lock);
+ raw_spin_unlock(&src_lock);
}
void imx_set_cpu_jump(int cpu, void *jump_addr)
{
- spin_lock(&src_lock);
+ raw_spin_lock(&src_lock);
cpu = cpu_logical_map(cpu);
if (cpu_is_imx7d())
writel_relaxed(__pa_symbol(jump_addr),
@@ -119,7 +119,7 @@ void imx_set_cpu_jump(int cpu, void *jump_addr)
else
writel_relaxed(__pa_symbol(jump_addr),
src_base + SRC_GPR1 + cpu * 8);
- spin_unlock(&src_lock);
+ raw_spin_unlock(&src_lock);
}
u32 imx_get_cpu_arg(int cpu)
@@ -172,7 +172,7 @@ void __init imx_src_init(void)
* force warm reset sources to generate cold reset
* for a more reliable restart
*/
- spin_lock(&src_lock);
+ raw_spin_lock(&src_lock);
val = readl_relaxed(src_base + SRC_SCR);
/* bit 4 is m4c_non_sclr_rst on i.MX6SX */
@@ -184,7 +184,7 @@ void __init imx_src_init(void)
val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
writel_relaxed(val, src_base + SRC_SCR);
- spin_unlock(&src_lock);
+ raw_spin_unlock(&src_lock);
}
static const struct of_device_id imx_src_dt_ids[] = {
--
2.25.1
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