Hi Bruce, Please find below the yocto-kernel-cache patch. Request you to merge this patch in yocto-kernel-cache yocto-6.1 branch. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ V2 Change log: Following changes done in the yocto-kernel-cache BSP config file: Removed: CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y CONFIG_CFS_BANDWIDTH=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y CONFIG_JUMP_LABEL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_INET=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_BLK_DEV_LOOP=y CONFIG_USB_STORAGE=m CONFIG_SPARSEMEM_MANUAL=y CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_FANOTIFY=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_PRINTK_TIME=y CONFIG_DEBUG_FS=y CONFIG_SCHED_STACK_END_CHECK=y CONFIG_SOFTLOCKUP_DETECTOR=y CONFIG_WQ_WATCHDOG=y CONFIG_STACKTRACE=y CONFIG_STRICT_DEVMEM=y CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="earlycon=sbi root=/dev/mmcblk0p3 rootwait uio_pdrv_genirq.of_id=generic-uio" CONFIG_INPUT_JOYDEV=m CONFIG_INPUT_JOYSTICK=y CONFIG_JOYSTICK_SENSEHAT=m CONFIG_AUXDISPLAY=y CONFIG_SENSEHAT_DISPLAY=m CONFIG_HTS221=m CONFIG_IIO_ST_PRESS=m CONFIG_IIO_ST_LSM6DSX=m CONFIG_IIO_ST_MAGN_3AXIS=m CONFIG_IIO_ST_MAGN_SPI_3AXIS=n CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=n CONFIG_MTD_UBI=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_UBIFS_FS=y
Added: CONFIG_NR_CPUS=4 Modifed to static: CONFIG_SPI_SPIDEV=y CONFIG_PMBUS=y CONFIG_USB_ACM=y CONFIG_USB_SERIAL=y CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_CTRL=y CONFIG_RPMSG_TTY=y CONFIG_IIO=y CONFIG_IIO_SW_DEVICE=y CONFIG_IIO_SW_TRIGGER=y CONFIG_PAC193X=y ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ >From 551ea4aa5214e270265dd23d1dd1b5844fe377fc Mon Sep 17 00:00:00 2001 From: "Saravanan.K.S" <[email protected]> Date: Tue, 7 Nov 2023 10:46:02 +0000 Subject: [PATCH] microchip-polarfire-soc: add configure file for microchip-polarfire-soc BSP in kernel-cache Signed-off-by: Saravanan.K.S <[email protected]> --- .../microchip-polarfire-soc-preempt-rt.scc | 8 ++ .../microchip-polarfire-soc-standard.scc | 8 ++ .../microchip-polarfire-soc.cfg | 106 ++++++++++++++++++ .../microchip-polarfire-soc.scc | 5 + 4 files changed, 127 insertions(+) create mode 100755 bsp/microchip-polarfire-soc/microchip-polarfire-soc-preempt-rt.scc create mode 100755 bsp/microchip-polarfire-soc/microchip-polarfire-soc-standard.scc create mode 100644 bsp/microchip-polarfire-soc/microchip-polarfire-soc.cfg create mode 100755 bsp/microchip-polarfire-soc/microchip-polarfire-soc.scc diff --git a/bsp/microchip-polarfire-soc/microchip-polarfire-soc-preempt-rt.scc b/bsp/microchip-polarfire-soc/microchip-polarfire-soc-preempt-rt.scc new file mode 100755 index 00000000..ce1bc266 --- /dev/null +++ b/bsp/microchip-polarfire-soc/microchip-polarfire-soc-preempt-rt.scc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: MIT +define KMACHINE microchip-polarfire-soc +define KTYPE preempt-rt +define KARCH riscv64 + +include ktypes/preempt-rt + +include microchip-polarfire-soc.scc diff --git a/bsp/microchip-polarfire-soc/microchip-polarfire-soc-standard.scc b/bsp/microchip-polarfire-soc/microchip-polarfire-soc-standard.scc new file mode 100755 index 00000000..21d69d5a --- /dev/null +++ b/bsp/microchip-polarfire-soc/microchip-polarfire-soc-standard.scc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: MIT +define KMACHINE microchip-polarfire-soc +define KTYPE standard +define KARCH riscv64 + +include ktypes/standard + +include microchip-polarfire-soc.scc diff --git a/bsp/microchip-polarfire-soc/microchip-polarfire-soc.cfg b/bsp/microchip-polarfire-soc/microchip-polarfire-soc.cfg new file mode 100644 index 00000000..ba02f3c0 --- /dev/null +++ b/bsp/microchip-polarfire-soc/microchip-polarfire-soc.cfg @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: MIT +.......................................................................... +. WARNING +. +. This file is a kernel configuration fragment, and not a full kernel +. configuration file. The final kernel configuration is made up of +. an assembly of processed fragments, each of which is designed to +. capture a specific part of the final configuration (e.g. platform +. configuration, feature configuration, and board specific hardware +. configuration). For more information on kernel configuration, please +. consult the product documentation. +. +.......................................................................... + +# mpfs_defconfig +CONFIG_SOC_MICROCHIP_POLARFIRE=y +CONFIG_SMP=y +CONFIG_NR_CPUS=4 +CONFIG_PCI=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCIE_MICROCHIP_HOST=y +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_CONFIGFS=y +CONFIG_BLK_DEV_NVME=y +CONFIG_BLK_DEV_SD=y +CONFIG_ATA=y +CONFIG_NETDEVICES=y +CONFIG_MACB=y +CONFIG_MICROSEMI_PHY=y +CONFIG_MICREL_PHY=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_POLARFIRE_SOC=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MICROCHIP_CORE=y +CONFIG_SPI=y +CONFIG_SPI_MICROCHIP_CORE=y +CONFIG_SPI_MICROCHIP_CORE_QSPI=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_POLARFIRE_SOC=y +CONFIG_PMBUS=y +CONFIG_POWER_RESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_ACM=y +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_POLARFIRE_SOC=y +CONFIG_USB_INVENTRA_DMA=y +CONFIG_USB_SERIAL=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_CADENCE=y +CONFIG_MMC_SPI=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_POLARFIRE_SOC=y +CONFIG_DMADEVICES=y +CONFIG_SF_PDMA=y +CONFIG_MPFS_DMA_PROXY=y +CONFIG_UIO=y +CONFIG_UIO_PDRV_GENIRQ=y +CONFIG_UIO_DMEM_GENIRQ=y +CONFIG_UIO_MICROCHIP_CAN=y +CONFIG_UIO_MICROCHIP_DMA=y +CONFIG_MAILBOX=y +CONFIG_POLARFIRE_SOC_MAILBOX=y +CONFIG_MIV_IHC=y +CONFIG_REMOTEPROC=y +CONFIG_REMOTEPROC_CDEV=y +CONFIG_MIV_REMOTEPROC=y +CONFIG_RPMSG_CHAR=y +CONFIG_RPMSG_CTRL=y +CONFIG_RPMSG_MIV=y +CONFIG_RPMSG_TTY=y +CONFIG_RPMSG_VIRTIO=y +CONFIG_POLARFIRE_SOC_SYS_CTRL=y +CONFIG_POLARFIRE_SOC_GENERIC_SERVICE=m +CONFIG_SIFIVE_CCACHE=y +CONFIG_IIO=y +CONFIG_IIO_SW_DEVICE=y +CONFIG_IIO_SW_TRIGGER=y +CONFIG_PAC193X=y +CONFIG_PWM=y +CONFIG_PWM_MICROCHIP_CORE=y +CONFIG_RESET_CONTROLLER=y +CONFIG_FPGA=y +CONFIG_FPGA_BRIDGE=y +CONFIG_FPGA_REGION=y +CONFIG_FPGA_MGR_MICROCHIP_AUTO_UPDATE=y +CONFIG_FPGA_MGR_MICROCHIP_SPI=y diff --git a/bsp/microchip-polarfire-soc/microchip-polarfire-soc.scc b/bsp/microchip-polarfire-soc/microchip-polarfire-soc.scc new file mode 100755 index 00000000..3a8b9182 --- /dev/null +++ b/bsp/microchip-polarfire-soc/microchip-polarfire-soc.scc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: MIT +kconf hardware microchip-polarfire-soc.cfg + +include cfg/usb-mass-storage.scc +include cfg/fs/flash_fs.scc -- 2.40.0 Thanks Saravanan ________________________________ From: Kevin Hao Sent: Friday, November 10, 2023 6:16 PM To: Kadambathur Subramaniyam, Saravanan Cc: Bruce Ashfield; [email protected]; G Pillai, Hari Subject: Re: [V2-revised] Microchip polarfire SoC - yocto-kernel-cache & linux-yocto V2 patch. On Fri, Nov 10, 2023 at 12:21:49PM +0000, Kadambathur Subramaniyam, Saravanan wrote: > //Changed subject line > Hi Bruce > We closed all the internal review comments which Kexin mentioned in his below > email. He approved the updated patch. Hi Saravanan, For the kernel cache change, since there is only one patch, you should sent it as standalone patch. It is more easy to comment than a pull request. Please also remember to summarize the changes compare to the previous version. For the kernel patches, I suggest you resent the pull request. Please make sure to use plain text instead of HTML in your pull request. Thanks, Kevin
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