merged.

Bruce

In message: [linux-yocto][v5.15/standard/intel-sdk-5.15/intel-socfpga && 
v5.15/standard/preempt-rt/intel-sdk-5.15/intel-socfpga][PATCH 1/1] arch: arm64: 
dts: improve the overlay used to updating FPGA image
on 25/12/2023 Liwei Song wrote:

> From: Meng Li <[email protected]>
> 
> - remove unnecessary #address-cells and #size-cells property
> - correct #address-cells and #size-cells property
> 
> Signed-off-by: Meng Li <[email protected]>
> Signed-off-by: Bruce Ashfield <[email protected]>
> Signed-off-by: Liwei Song <[email protected]>
> ---
>  .../arm64/boot/dts/altera/socfpga_stratix10_fpga_update.dts | 6 ++----
>  arch/arm64/boot/dts/intel/socfpga_agilex_fpga_update.dts    | 6 ++----
>  2 files changed, 4 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_fpga_update.dts 
> b/arch/arm64/boot/dts/altera/socfpga_stratix10_fpga_update.dts
> index c7811cc92091..a224909a4834 100644
> --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_fpga_update.dts
> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_fpga_update.dts
> @@ -3,11 +3,9 @@
>  / {
>       fragment@0 {
>               target-path = "/soc/base_fpga_region";
> -             #address-cells = <1>;
> -             #size-cells = <1>;
>               __overlay__ {
> -                     #address-cells = <1>;
> -                     #size-cells = <1>;
> +                     #address-cells = <2>;
> +                     #size-cells = <2>;
>  
>                       firmware-name = "soc_s10_fpga_config.rbf";
>                       config-complete-timeout-us = <2000000>;
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_fpga_update.dts 
> b/arch/arm64/boot/dts/intel/socfpga_agilex_fpga_update.dts
> index 5383e02bfc35..2e91eddc50ec 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex_fpga_update.dts
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_fpga_update.dts
> @@ -3,11 +3,9 @@
>  / {
>       fragment@0 {
>               target-path = "/soc/base_fpga_region";
> -             #address-cells = <1>;
> -             #size-cells = <1>;
>               __overlay__ {
> -                     #address-cells = <1>;
> -                     #size-cells = <1>;
> +                     #address-cells = <2>;
> +                     #size-cells = <2>;
>  
>                       firmware-name = "soc_agilex_fpga_config.rbf";
>                       config-complete-timeout-us = <2000000>;
> -- 
> 2.40.0
> 
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