From: harish h <haris...@windriver.com> This adds the cfg & scc files to support microchip polarfire soc. This refers to scc and cfg files on previous branch yocto-6.1.
Signed-off-by: harish h <haris...@windriver.com> --- .../microchip-polarfire-soc-preempt-rt.scc | 8 ++ .../microchip-polarfire-soc-standard.scc | 8 ++ .../microchip-polarfire-soc.cfg | 117 ++++++++++++++++++ .../microchip-polarfire-soc.scc | 5 + 4 files changed, 138 insertions(+) create mode 100755 bsp/microchip-polarfire-soc/microchip-polarfire-soc-preempt-rt.scc create mode 100755 bsp/microchip-polarfire-soc/microchip-polarfire-soc-standard.scc create mode 100644 bsp/microchip-polarfire-soc/microchip-polarfire-soc.cfg create mode 100755 bsp/microchip-polarfire-soc/microchip-polarfire-soc.scc diff --git a/bsp/microchip-polarfire-soc/microchip-polarfire-soc-preempt-rt.scc b/bsp/microchip-polarfire-soc/microchip-polarfire-soc-preempt-rt.scc new file mode 100755 index 00000000..ce1bc266 --- /dev/null +++ b/bsp/microchip-polarfire-soc/microchip-polarfire-soc-preempt-rt.scc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: MIT +define KMACHINE microchip-polarfire-soc +define KTYPE preempt-rt +define KARCH riscv64 + +include ktypes/preempt-rt + +include microchip-polarfire-soc.scc diff --git a/bsp/microchip-polarfire-soc/microchip-polarfire-soc-standard.scc b/bsp/microchip-polarfire-soc/microchip-polarfire-soc-standard.scc new file mode 100755 index 00000000..21d69d5a --- /dev/null +++ b/bsp/microchip-polarfire-soc/microchip-polarfire-soc-standard.scc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: MIT +define KMACHINE microchip-polarfire-soc +define KTYPE standard +define KARCH riscv64 + +include ktypes/standard + +include microchip-polarfire-soc.scc diff --git a/bsp/microchip-polarfire-soc/microchip-polarfire-soc.cfg b/bsp/microchip-polarfire-soc/microchip-polarfire-soc.cfg new file mode 100644 index 00000000..97d3a88e --- /dev/null +++ b/bsp/microchip-polarfire-soc/microchip-polarfire-soc.cfg @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: MIT +.......................................................................... +. WARNING +. +. This file is a kernel configuration fragment, and not a full kernel +. configuration file. The final kernel configuration is made up of +. an assembly of processed fragments, each of which is designed to +. capture a specific part of the final configuration (e.g. platform +. configuration, feature configuration, and board specific hardware +. configuration). For more information on kernel configuration, please +. consult the product documentation. +. +.......................................................................... + +# mpfs_defconfig +CONFIG_SOC_MICROCHIP_POLARFIRE=y +CONFIG_SMP=y +CONFIG_NR_CPUS=4 +CONFIG_PCI=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCIE_MICROCHIP_HOST=y +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_CONFIGFS=y +CONFIG_BLK_DEV_NVME=y +CONFIG_BLK_DEV_SD=y +CONFIG_ATA=y +CONFIG_NETDEVICES=y +CONFIG_MACB=y +CONFIG_MICROSEMI_PHY=y +CONFIG_MICREL_PHY=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_RISCV_SBI_V01=y +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_POLARFIRE_SOC=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MICROCHIP_CORE=y +CONFIG_SPI=y +CONFIG_SPI_MICROCHIP_CORE=y +CONFIG_SPI_MICROCHIP_CORE_QSPI=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_POLARFIRE_SOC=y +CONFIG_PMBUS=y +CONFIG_POWER_RESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_ACM=y +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_POLARFIRE_SOC=y +CONFIG_USB_INVENTRA_DMA=y +CONFIG_USB_SERIAL=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_CADENCE=y +CONFIG_MMC_SPI=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_POLARFIRE_SOC=y +CONFIG_DMADEVICES=y +CONFIG_SF_PDMA=y +CONFIG_MPFS_DMA_PROXY=y +CONFIG_UIO=y +CONFIG_UIO_PDRV_GENIRQ=y +CONFIG_UIO_DMEM_GENIRQ=y +CONFIG_UIO_MICROCHIP_CAN=y +CONFIG_UIO_MICROCHIP_DMA=y +CONFIG_MAILBOX=y +CONFIG_POLARFIRE_SOC_MAILBOX=y +CONFIG_MIV_IHC=y +CONFIG_REMOTEPROC=y +CONFIG_REMOTEPROC_CDEV=y +CONFIG_MIV_REMOTEPROC=y +CONFIG_RPMSG_CHAR=y +CONFIG_RPMSG_CTRL=y +CONFIG_RPMSG_TTY=y +CONFIG_RPMSG_VIRTIO=y +CONFIG_POLARFIRE_SOC_SYS_CTRL=y +CONFIG_POLARFIRE_SOC_GENERIC_SERVICE=m +CONFIG_SIFIVE_CCACHE=y +CONFIG_IIO=y +CONFIG_IIO_SW_DEVICE=y +CONFIG_IIO_SW_TRIGGER=y +CONFIG_PAC193X=y +CONFIG_PWM=y +CONFIG_PWM_MICROCHIP_CORE=y +CONFIG_RESET_CONTROLLER=y +CONFIG_FPGA=y +CONFIG_FPGA_BRIDGE=y +CONFIG_FPGA_REGION=y +CONFIG_FPGA_MGR_MICROCHIP_AUTO_UPDATE=y +CONFIG_FPGA_MGR_MICROCHIP_SPI=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_VFIO=y +CONFIG_VFIO_PCI=y +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_ETH=y +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_MUSB_HOST=n +CONFIG_USB_MUSB_GADGET=n +CONFIG_USB_MUSB_DUAL_ROLE=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_GADGETFS=y diff --git a/bsp/microchip-polarfire-soc/microchip-polarfire-soc.scc b/bsp/microchip-polarfire-soc/microchip-polarfire-soc.scc new file mode 100755 index 00000000..3a8b9182 --- /dev/null +++ b/bsp/microchip-polarfire-soc/microchip-polarfire-soc.scc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: MIT +kconf hardware microchip-polarfire-soc.cfg + +include cfg/usb-mass-storage.scc +include cfg/fs/flash_fs.scc -- 2.25.1
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