From: Kevin Hao <kexin....@windriver.com>
The merge commit 82bab3e1d163 ("Merge branch 'v5.15/standard/base' into
v5.15/standard/preempt-rt/base") introduced a lot of unrelated changes.
These affected files should have the same content in both the standard
and rt kernels. The changes in this patch is almost the same as the
output of the following command:
rediff <(git show 82bab3e1d163
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | \
sed -e "s#^++\([^-+]\+\|$\)#-\1#" -e "s#^--\([^-+]\+\|$\)#+\1#" -e "s#^ #
#" \
-e "s#^[-+] # #" -e "s#^ [-+]# #" -e "s#^diff --cc#diff --git#" -e "s#^@@@
[0-9,-]\+#@@#" \
-e "s#@@@#@@#")
Signed-off-by: Kevin Hao <kexin....@windriver.com>
---
Hi Bruce,
These unrelated changes were introduced by a merge commit on rt base branch,
but we can't simply cherry-pick this patch on rt base branch, and then
merge it into all the rt branches because some of rt branches don't
need these changes. So we have to manually apply this patch to
all the following rt branches:
v5.15/standard/preempt-rt/bcm-2xxx-rpi
v5.15/standard/preempt-rt/cn-sdkv5.15/octeon
v5.15/standard/preempt-rt/cn-sdkv5.4/octeon
v5.15/standard/preempt-rt/intel-sdk-5.15/intel-socfpga
v5.15/standard/preempt-rt/nxp-sdk-5.10/nxp-s32g
v5.15/standard/preempt-rt/nxp-sdk-5.15/nxp-s32g
v5.15/standard/preempt-rt/sdkv5.10/axxia
v5.15/standard/preempt-rt/sdkv5.15/xlnx-soc
v5.15/standard/preempt-rt/ti-sdk-5.10/ti-j72xx
v5.15/standard/preempt-rt/x86
---
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 249 ++++--------------------
1 file changed, 34 insertions(+), 215 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index 96d35865b968..685e9b83d42b 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -34,64 +34,24 @@ conn_ipg_clk: clock-conn-ipg {
clock-output-names = "conn_ipg_clk";
};
- conn_bch_clk: clock-conn-bch {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <400000000>;
- clock-output-names = "conn_bch_clk";
- };
-
- usbotg1: usb@5b0d0000 {
- compatible = "fsl,imx8qm-usb", "fsl,imx7ulp-usb",
- "fsl,imx27-usb";
- reg = <0x5b0d0000 0x200>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
- fsl,usbphy = <&usbphy1>;
- fsl,usbmisc = <&usbmisc1 0>;
- clocks = <&usb2_lpcg 0>;
- ahb-burst-config = <0x0>;
- tx-burst-size-dword = <0x10>;
- rx-burst-size-dword = <0x10>;
- power-domains = <&pd IMX_SC_R_USB_0>;
- status = "disabled";
- };
-
- usbmisc1: usbmisc@5b0d0200 {
- #index-cells = <1>;
- compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc";
- reg = <0x5b0d0200 0x200>;
- };
-
- usbphy1: usbphy@0x5b100000 {
- compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy",
- "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
- reg = <0x5b100000 0x1000>;
- clocks = <&usb2_lpcg 1>;
- power-domains = <&pd IMX_SC_R_USB_0_PHY>;
- status = "disabled";
- };
-
usdhc1: mmc@5b010000 {
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
- clocks = <&sdhc0_lpcg 1>,
- <&sdhc0_lpcg 0>,
- <&sdhc0_lpcg 2>;
- clock-names = "ipg", "per", "ahb";
+ clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
+ <&sdhc0_lpcg IMX_LPCG_CLK_5>,
+ <&sdhc0_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg", "ahb", "per";
power-domains = <&pd IMX_SC_R_SDHC_0>;
- fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
status = "disabled";
};
usdhc2: mmc@5b020000 {
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b020000 0x10000>;
- clocks = <&sdhc1_lpcg 1>,
- <&sdhc1_lpcg 0>,
- <&sdhc1_lpcg 2>;
- clock-names = "ipg", "per", "ahb";
+ clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>,
+ <&sdhc1_lpcg IMX_LPCG_CLK_5>,
+ <&sdhc1_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg", "ahb", "per";
power-domains = <&pd IMX_SC_R_SDHC_1>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
@@ -101,13 +61,11 @@ usdhc2: mmc@5b020000 {
usdhc3: mmc@5b030000 {
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b030000 0x10000>;
- clocks = <&sdhc2_lpcg 1>,
- <&sdhc2_lpcg 0>,
- <&sdhc2_lpcg 2>;
- clock-names = "ipg", "per", "ahb";
+ clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>,
+ <&sdhc2_lpcg IMX_LPCG_CLK_5>,
+ <&sdhc2_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg", "ahb", "per";
power-domains = <&pd IMX_SC_R_SDHC_2>;
- fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
status = "disabled";
};
@@ -117,12 +75,11 @@ fec1: ethernet@5b040000 {
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&enet0_lpcg 4>,
- <&enet0_lpcg 2>,
- <&enet0_lpcg 3>,
- <&enet0_lpcg 0>,
- <&enet0_lpcg 1>;
- clock-names = "ipg", "ahb", "enet_clk_ref", "ptp",
"enet_2x_txclk";
+ clocks = <&enet0_lpcg IMX_LPCG_CLK_4>,
+ <&enet0_lpcg IMX_LPCG_CLK_2>,
+ <&enet0_lpcg IMX_LPCG_CLK_3>,
+ <&enet0_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
assigned-clock-rates = <250000000>, <125000000>;
@@ -138,12 +95,11 @@ fec2: ethernet@5b050000 {
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&enet1_lpcg 4>,
- <&enet1_lpcg 2>,
- <&enet1_lpcg 3>,
- <&enet1_lpcg 0>,
- <&enet1_lpcg 1>;
- clock-names = "ipg", "ahb", "enet_clk_ref", "ptp",
"enet_2x_txclk";
+ clocks = <&enet1_lpcg IMX_LPCG_CLK_4>,
+ <&enet1_lpcg IMX_LPCG_CLK_2>,
+ <&enet1_lpcg IMX_LPCG_CLK_3>,
+ <&enet1_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
assigned-clock-rates = <250000000>, <125000000>;
@@ -153,56 +109,6 @@ fec2: ethernet@5b050000 {
status = "disabled";
};
- usb3_phy: usb-phy@5b160000 {
- compatible = "nxp,salvo-phy";
- reg = <0x5B160000 0x40000>;
- clocks = <&usb3_lpcg 4>;
- clock-names = "salvo_phy_clk";
- power-domains = <&pd IMX_SC_R_USB_2_PHY>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- usbotg3: usb@5b110000 {
- compatible = "fsl,imx8qm-usb3";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- reg = <0x5B110000 0x10000>;
- clocks = <&usb3_lpcg 1>,
- <&usb3_lpcg 0>,
- <&usb3_lpcg 5>,
- <&usb3_lpcg 2>,
- <&usb3_lpcg 3>;
- clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk",
- "usb3_ipg_clk", "usb3_core_pclk";
- assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>,
- <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>,
- <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
- assigned-clock-rates = <125000000>, <12000000>, <250000000>;
- power-domains = <&pd IMX_SC_R_USB_2>;
- status = "disabled";
-
- usbotg3_cdns3: usb@5b120000 {
- compatible = "cdns,usb3";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host", "peripheral", "otg", "wakeup";
- reg = <0x5B130000 0x10000>, /* memory area for HOST
registers */
- <0x5B140000 0x10000>, /* memory area for
DEVICE registers */
- <0x5B120000 0x10000>; /* memory area for
OTG/DRD registers */
- reg-names = "xhci", "dev", "otg";
- phys = <&usb3_phy>;
- phy-names = "cdns3,usb3-phy";
- status = "disabled";
- };
- };
-
/* LPCG clocks */
sdhc0_lpcg: clock-controller@5b200000 {
compatible = "fsl,imx8qxp-lpcg";
@@ -210,7 +116,8 @@ sdhc0_lpcg: clock-controller@5b200000 {
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
<&conn_ipg_clk>, <&conn_axi_clk>;
- bit-offset = <0 16 20>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
+ <IMX_LPCG_CLK_5>;
clock-output-names = "sdhc0_lpcg_per_clk",
"sdhc0_lpcg_ipg_clk",
"sdhc0_lpcg_ahb_clk";
@@ -223,7 +130,8 @@ sdhc1_lpcg: clock-controller@5b210000 {
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>,
<&conn_ipg_clk>, <&conn_axi_clk>;
- bit-offset = <0 16 20>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
+ <IMX_LPCG_CLK_5>;
clock-output-names = "sdhc1_lpcg_per_clk",
"sdhc1_lpcg_ipg_clk",
"sdhc1_lpcg_ahb_clk";
@@ -236,7 +144,8 @@ sdhc2_lpcg: clock-controller@5b220000 {
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>,
<&conn_ipg_clk>, <&conn_axi_clk>;
- bit-offset = <0 16 20>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
+ <IMX_LPCG_CLK_5>;
clock-output-names = "sdhc2_lpcg_per_clk",
"sdhc2_lpcg_ipg_clk",
"sdhc2_lpcg_ahb_clk";
@@ -253,7 +162,9 @@ enet0_lpcg: clock-controller@5b230000 {
<&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
<&conn_ipg_clk>,
<&conn_ipg_clk>;
- bit-offset = <0 4 8 12 16 20>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
+ <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
+ <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
clock-output-names = "enet0_lpcg_timer_clk",
"enet0_lpcg_txc_sampling_clk",
"enet0_lpcg_ahb_clk",
@@ -273,7 +184,9 @@ enet1_lpcg: clock-controller@5b240000 {
<&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>,
<&conn_ipg_clk>,
<&conn_ipg_clk>;
- bit-offset = <0 4 8 12 16 20>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
+ <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
+ <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
clock-output-names = "enet1_lpcg_timer_clk",
"enet1_lpcg_txc_sampling_clk",
"enet1_lpcg_ahb_clk",
@@ -282,98 +195,4 @@ enet1_lpcg: clock-controller@5b240000 {
"enet1_lpcg_ipg_s_clk";
power-domains = <&pd IMX_SC_R_ENET_1>;
};
-
- usb2_lpcg: clock-controller@5b270000 {
- compatible = "fsl,imx8qxp-lpcg";
- reg = <0x5b270000 0x10000>;
- #clock-cells = <1>;
- clocks = <&conn_ahb_clk>, <&conn_ipg_clk>;
- bit-offset = <24 28>;
- clock-output-names = "usboh3_ahb_clk",
- "usboh3_phy_ipg_clk";
- power-domains = <&pd IMX_SC_R_USB_0_PHY>;
- };
-
- usb3_lpcg: clock-controller@5b280000 {
- compatible = "fsl,imx8qxp-lpcg";
- reg = <0x5b280000 0x10000>;
- #clock-cells = <1>;
- bit-offset = <0 4 16 20 24 28>;
- clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>,
- <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>,
- <&conn_ipg_clk>,
- <&conn_ipg_clk>,
- <&conn_ipg_clk>,
- <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
- clock-output-names = "usb3_app_clk",
- "usb3_lpm_clk",
- "usb3_ipg_clk",
- "usb3_core_pclk",
- "usb3_phy_clk",
- "usb3_aclk";
- power-domains = <&pd IMX_SC_R_USB_2>;
- };
-
- rawnand_0_lpcg: clock-controller@5b290000 {
- compatible = "fsl,imx8qxp-lpcg";
- reg = <0x5b290000 0x4>;
- #clock-cells = <1>;
- clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_PER>,
- <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>,
- <&conn_axi_clk>,
- <&conn_axi_clk>;
- bit-offset = <0 4 16 20>;
- clock-output-names = "bch_clk",
- "gpmi_clk",
- "gpmi_apb_clk",
- "bch_apb_clk";
- power-domains = <&pd IMX_SC_R_NAND>;
- };
-
- rawnand_4_lpcg: clock-controller@5b290004 {
- compatible = "fsl,imx8qxp-lpcg";
- reg = <0x5b290004 0x10000>;
- #clock-cells = <1>;
- clocks = <&conn_axi_clk>;
- bit-offset = <16>;
- clock-output-names = "apbhdma_hclk";
- power-domains = <&pd IMX_SC_R_NAND>;
- };
-
- dma_apbh: dma-apbh@5b810000 {
- compatible = "fsl,imx28-dma-apbh";
- reg = <0x5b810000 0x2000>;
- interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
- #dma-cells = <1>;
- dma-channels = <4>;
- clocks = <&rawnand_4_lpcg 0>;
- clock-names = "apbhdma_hclk";
- power-domains = <&pd IMX_SC_R_NAND>;
- };
-
- gpmi: gpmi-nand@5b812000{
- compatible = "fsl,imx8qxp-gpmi-nand";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x5b812000 0x2000>, <0x5b814000 0x2000>;
- reg-names = "gpmi-nand", "bch";
- interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "bch";
- clocks = <&rawnand_0_lpcg 1>,
- <&rawnand_0_lpcg 2>,
- <&rawnand_0_lpcg 0>,
- <&rawnand_0_lpcg 3>;
- clock-names = "gpmi_clk", "gpmi_apb_clk",
- "bch_clk", "bch_apb_clk";
- dmas = <&dma_apbh 0>;
- dma-names = "rx-tx";
- power-domains = <&pd IMX_SC_R_NAND>;
- assigned-clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>;
- assigned-clock-rates = <50000000>;
- status = "disabled";
- };
};
---
base-commit: af7b8b6bd080db6a6a5398ec88bb8985f7402f08
change-id: 20240815-v5-15-rt-dtb-058963c09a10
Best regards,
--
Kevin Hao <haoke...@gmail.com>
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