From: Jiang Lu <lu.ji...@windriver.com>
ACP34xx GPIO block is consist of 2 ARM PrimeCell GPIO (PL061). Each
provide 8 gpio pins. The pins 4, 8, 11, 13(index starting from 0)
are reserved for some hardware.
The interrupt lines for each gpio (GPIOMIS[7:0]) are not connected
to PIC, it does not match the gpiolib framework's requirement.
As result, in dts for ACP34xx, the node for pl061 gpio should not
contain irq entry.
The driver update pl061 driver to use ACP34xx specific io routines,
and load init-pin map from device-tree to reserve certain pins for
hardware.
Signed-off-by: Jiang Lu <lu.ji...@windriver.com>
---
drivers/gpio/gpio-pl061.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c
index a87b4d4..9d35136 100644
--- a/drivers/gpio/gpio-pl061.c
+++ b/drivers/gpio/gpio-pl061.c
@@ -30,6 +30,13 @@
#include <linux/slab.h>
#include <linux/pm.h>
+#ifdef CONFIG_PPC
+#define readb(addr) ((char)readl(addr))
+#define writeb(b, addr) writel(b, addr)
+
+#define GPIO_AFSEL 0x420
+#endif
+
#define GPIODIR 0x400
#define GPIOIS 0x404
#define GPIOIBE 0x408
@@ -440,6 +447,13 @@ static int __devinit pl061_of_probe(struct platform_device
*ofdev)
if (ret < 0)
return ret;
+
+ prop = of_get_property(ofdev->dev.of_node, "pins-map", &len);
+ if (!prop || len < sizeof(*prop))
+ dev_warn(&ofdev->dev, "no 'pins-map' property\n");
+ else
+ writeb(*prop, chip->base + GPIO_AFSEL);
+
return 0;
}
--
1.8.3
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