Re: [linux-yocto] [PATCH 48/87] ppc/47x: add cputable entries for ACP 34xx

Mon, 27 May 2013 12:10:55 -0700 

On 13-05-27 12:56 PM, Paul Butler wrote:

From: Jiang Lu <[email protected]>

This is based on the cputable.c from LSI. Currently our kernel only
support ACP 3448 SoC. But all the ACP 34xx SoC are using a 476 core,
and just have minor differences. They also use the same reference
board. Adding these cpu entries in cputable will make our kernel
boot on all these 34xx silicons.


This comment should be tweaked. The statement about "our kernel", should
indicate that only the tested BSPs are teh ACP 3488, or something of
that nature.

Cheers,

Bruce



Signed-off-by: Kevin Hao <[email protected]>
---
  arch/powerpc/include/asm/reg.h |  1 +
  arch/powerpc/kernel/cputable.c | 58 ++++++++++++++++++++++++++++++++++++------
  arch/powerpc/kernel/head_44x.S |  3 +++
  3 files changed, 54 insertions(+), 8 deletions(-)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index cae0ed7..b40b2f5 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -957,6 +957,7 @@
  #define PVR_405GP     0x40110000
  #define PVR_476               0x11a52000
  #define PVR_476FPE    0x7ff50000
+#define PVR_476X2      0x11b22080
  #define PVR_STB03XXX  0x40310000
  #define PVR_NP405H    0x41410000
  #define PVR_NP405L    0x41610000
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 455faa3..88479f1 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1831,9 +1831,23 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .platform               = "ppc440",
        },
        { /* 476 DD2 core */
+               .pvr_mask               = 0x800fffff,
+               .pvr_value              = 0x00052080,
+               .cpu_name               = "476, DD2",
+               .cpu_features           = CPU_FTRS_47X | CPU_FTR_476_DD2,
+               .cpu_user_features      = COMMON_USER_BOOKE |
+                       PPC_FEATURE_HAS_FPU,
+               .mmu_features           = MMU_FTR_TYPE_47x |
+                       MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
+               .icache_bsize           = 32,
+               .dcache_bsize           = 128,
+               .machine_check          = machine_check_47x,
+               .platform               = "ppc470",
+       },
+       { /* X2 DD2 core */
                .pvr_mask               = 0xffffffff,
-               .pvr_value              = 0x11a52080,
-               .cpu_name               = "476",
+               .pvr_value              = 0x11b22080,
+               .cpu_name               = "476, X2 DD2",
                .cpu_features           = CPU_FTRS_47X | CPU_FTR_476_DD2,
                .cpu_user_features      = COMMON_USER_BOOKE |
                        PPC_FEATURE_HAS_FPU,
@@ -1859,9 +1873,37 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .platform               = "ppc470",
        },
        { /* 476 iss */
-               .pvr_mask               = 0xffff0000,
-               .pvr_value              = 0x00050000,
-               .cpu_name               = "476",
+               .pvr_mask               = 0xffffffff,
+               .pvr_value              = 0x12b520c0,
+               .cpu_name                               = "476",
+               .cpu_features           = CPU_FTRS_47X | CPU_FTR_476_DD2,
+               .cpu_user_features      = COMMON_USER_BOOKE |
+                       PPC_FEATURE_HAS_FPU,
+               .mmu_features           = MMU_FTR_TYPE_47x |
+                       MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
+               .icache_bsize           = 32,
+               .dcache_bsize           = 128,
+               .machine_check          = machine_check_47x,
+               .platform               = "ppc470",
+       },
+       { /* 476 DD3 core */
+               .pvr_mask               = 0xffff20c0,
+               .pvr_value              = 0x11a520c0,
+               .cpu_name               = "476, DD3",
+               .cpu_features           = CPU_FTRS_47X,
+               .cpu_user_features      = COMMON_USER_BOOKE |
+                       PPC_FEATURE_HAS_FPU,
+               .mmu_features           = MMU_FTR_TYPE_47x |
+                       MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
+               .icache_bsize           = 32,
+               .dcache_bsize           = 128,
+               .machine_check          = machine_check_47x,
+               .platform               = "ppc470",
+       },
+       { /* 476 ACP25xx */
+               .pvr_mask               = 0x7ff520c1,
+               .pvr_value              = 0x7ff520c1,
+               .cpu_name               = "476, ACP25xx",
                .cpu_features           = CPU_FTRS_47X,
                .cpu_user_features      = COMMON_USER_BOOKE |
                        PPC_FEATURE_HAS_FPU,
@@ -1873,9 +1915,9 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .platform               = "ppc470",
        },
        { /* 476 others */
-               .pvr_mask               = 0xffff0000,
-               .pvr_value              = 0x11a50000,
-               .cpu_name               = "476",
+               .pvr_mask               = 0x800f0000,
+               .pvr_value              = 0x00050000,
+               .cpu_name               = "476, Other",
                .cpu_features           = CPU_FTRS_47X,
                .cpu_user_features      = COMMON_USER_BOOKE |
                        PPC_FEATURE_HAS_FPU,
diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
index 4aa3bd3..d1b0e79 100644
--- a/arch/powerpc/kernel/head_44x.S
+++ b/arch/powerpc/kernel/head_44x.S
@@ -824,6 +824,9 @@ _GLOBAL(init_cpu_state)
        /* We use the PVR to differenciate 44x cores from 476 */
        mfspr   r3,SPRN_PVR
        srwi    r3,r3,16
+       /* Some X2 chips had a PVR that doesn't conform to the standard */
+       cmplwi  cr0,r3,PVR_476X2@h
+       beq     head_start_47x
        cmplwi  cr0,r3,PVR_476FPE@h
        beq     head_start_47x
        cmplwi  cr0,r3,PVR_476@h



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