From: "Chang, Rebecca Swee Fun" <[email protected]>
dma: Baytrail has 1 DMA controller which can be PCI and ACPI enumerated. Signed-off-by: Chang, Rebecca Swee Fun <[email protected]> --- ...-add-support-for-Baytrail-DMA-controllers.patch | 1479 ++++++++++++++++++++ 1 file changed, 1479 insertions(+) create mode 100644 meta/cfg/kernel-cache/features/valleyisland-io/0005-dma-add-support-for-Baytrail-DMA-controllers.patch diff --git a/meta/cfg/kernel-cache/features/valleyisland-io/0005-dma-add-support-for-Baytrail-DMA-controllers.patch b/meta/cfg/kernel-cache/features/valleyisland-io/0005-dma-add-support-for-Baytrail-DMA-controllers.patch new file mode 100644 index 0000000..e0e40b4 --- /dev/null +++ b/meta/cfg/kernel-cache/features/valleyisland-io/0005-dma-add-support-for-Baytrail-DMA-controllers.patch @@ -0,0 +1,1479 @@ +dma: add support for Baytrail DMA controllers + +Intel Baytrail has 2 DMA controllers which can be PCI or ACPI enumerated. + +Signed-off-by: Chang, Rebecca Swee Fun <[email protected]> +--- + drivers/dma/Kconfig | 10 +- + drivers/dma/Makefile | 3 +- + drivers/dma/dw_dmac.c | 536 +++++++++++++++++++++++++++++++------------- + drivers/dma/dw_dmac_pci.c | 164 ++++++++++++++ + drivers/dma/dw_dmac_regs.h | 27 ++- + include/linux/dmaengine.h | 5 + + include/linux/dw_dmac.h | 43 ++-- + 7 files changed, 600 insertions(+), 188 deletions(-) + create mode 100644 drivers/dma/dw_dmac_pci.c + +diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig +index 93ea87e..ae706ca 100644 +--- a/drivers/dma/Kconfig ++++ b/drivers/dma/Kconfig +@@ -83,7 +83,6 @@ config INTEL_IOP_ADMA + + config DW_DMAC + tristate "Synopsys DesignWare AHB DMA support" +- depends on HAVE_CLK + select DMA_ENGINE + default y if CPU_AT32AP7000 + help +@@ -101,6 +100,15 @@ config DW_DMAC_BIG_ENDIAN_IO + + If unsure, use the default setting. + ++config DW_DMAC_PCI ++ tristate "Synopsys DesignWare AHB DMA support (PCI bus)" ++ depends on PCI ++ select DW_DMAC ++ help ++ Support the Synopsys DesignWare AHB DMA controller on the platfroms ++ that provide it as a PCI device. For example, Intel Medfield has ++ integrated this GPDMA controller. ++ + config AT_HDMAC + tristate "Atmel AHB DMA support" + depends on ARCH_AT91 +diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile +index 7428fea..89c0e966 100644 +--- a/drivers/dma/Makefile ++++ b/drivers/dma/Makefile +@@ -4,7 +4,6 @@ ccflags-$(CONFIG_DMADEVICES_VDEBUG) += -DVERBOSE_DEBUG + obj-$(CONFIG_DMA_ENGINE) += dmaengine.o + obj-$(CONFIG_DMA_VIRTUAL_CHANNELS) += virt-dma.o + obj-$(CONFIG_NET_DMA) += iovlock.o +-obj-$(CONFIG_INTEL_MID_DMAC) += intel_mid_dma.o + obj-$(CONFIG_DMATEST) += dmatest.o + obj-$(CONFIG_INTEL_IOATDMA) += ioat/ + obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o +@@ -12,6 +11,7 @@ obj-$(CONFIG_FSL_DMA) += fsldma.o + obj-$(CONFIG_MPC512X_DMA) += mpc512x_dma.o + obj-$(CONFIG_MV_XOR) += mv_xor.o + obj-$(CONFIG_DW_DMAC) += dw_dmac.o ++obj-$(CONFIG_DW_DMAC_PCI) += dw_dmac_pci.o + obj-$(CONFIG_AT_HDMAC) += at_hdmac.o + obj-$(CONFIG_MX3_IPU) += ipu/ + obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o +@@ -34,3 +34,4 @@ obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o + obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o + obj-$(CONFIG_DMA_OMAP) += omap-dma.o + obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o ++obj-$(CONFIG_INTEL_MID_DMAC) += intel_mid_dma.o +diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c +index 3e8ba02..426a107 100644 +--- a/drivers/dma/dw_dmac.c ++++ b/drivers/dma/dw_dmac.c +@@ -1,6 +1,5 @@ + /* +- * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on +- * AVR32 systems.) ++ * Core driver for the Synopsys DesignWare DMA Controller + * + * Copyright (C) 2007-2008 Atmel Corporation + * Copyright (C) 2010-2011 ST Microelectronics +@@ -9,11 +8,13 @@ + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ ++ + #include <linux/bitops.h> + #include <linux/clk.h> + #include <linux/delay.h> + #include <linux/dmaengine.h> + #include <linux/dma-mapping.h> ++#include <linux/dmapool.h> + #include <linux/init.h> + #include <linux/interrupt.h> + #include <linux/io.h> +@@ -46,15 +47,32 @@ static inline unsigned int dwc_get_sms(struct dw_dma_slave *slave) + return slave ? slave->src_master : 1; + } + ++#define SRC_MASTER 0 ++#define DST_MASTER 1 ++ ++static inline unsigned int dwc_get_master(struct dma_chan *chan, int master) ++{ ++ struct dw_dma *dw = to_dw_dma(chan->device); ++ struct dw_dma_slave *dws = chan->private; ++ unsigned int m; ++ ++ if (master == SRC_MASTER) ++ m = dwc_get_sms(dws); ++ else ++ m = dwc_get_dms(dws); ++ ++ return min_t(unsigned int, dw->nr_masters - 1, m); ++} ++ + #define DWC_DEFAULT_CTLLO(_chan) ({ \ +- struct dw_dma_slave *__slave = (_chan->private); \ + struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ + struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ +- int _dms = dwc_get_dms(__slave); \ +- int _sms = dwc_get_sms(__slave); \ +- u8 _smsize = __slave ? _sconfig->src_maxburst : \ ++ bool _is_slave = is_slave_direction(_dwc->direction); \ ++ int _dms = dwc_get_master(_chan, DST_MASTER); \ ++ int _sms = dwc_get_master(_chan, SRC_MASTER); \ ++ u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ + DW_DMA_MSIZE_16; \ +- u8 _dmsize = __slave ? _sconfig->dst_maxburst : \ ++ u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ + DW_DMA_MSIZE_16; \ + \ + (DWC_CTLL_DST_MSIZE(_dmsize) \ +@@ -72,15 +90,14 @@ static inline unsigned int dwc_get_sms(struct dw_dma_slave *slave) + */ + #define NR_DESCS_PER_CHANNEL 64 + +-/*----------------------------------------------------------------------*/ ++static inline unsigned int dwc_get_data_width(struct dma_chan *chan, int master) ++{ ++ struct dw_dma *dw = to_dw_dma(chan->device); + +-/* +- * Because we're not relying on writeback from the controller (it may not +- * even be configured into the core!) we don't need to use dma_pool. These +- * descriptors -- and associated data -- are cacheable. We do need to make +- * sure their dcache entries are written back before handing them off to +- * the controller, though. +- */ ++ return dw->data_width[dwc_get_master(chan, master)]; ++} ++ ++/*----------------------------------------------------------------------*/ + + static struct device *chan2dev(struct dma_chan *chan) + { +@@ -93,7 +110,7 @@ static struct device *chan2parent(struct dma_chan *chan) + + static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) + { +- return list_entry(dwc->active_list.next, struct dw_desc, desc_node); ++ return to_dw_desc(dwc->active_list.next); + } + + static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) +@@ -120,19 +137,6 @@ static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) + return ret; + } + +-static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc) +-{ +- struct dw_desc *child; +- +- list_for_each_entry(child, &desc->tx_list, desc_node) +- dma_sync_single_for_cpu(chan2parent(&dwc->chan), +- child->txd.phys, sizeof(child->lli), +- DMA_TO_DEVICE); +- dma_sync_single_for_cpu(chan2parent(&dwc->chan), +- desc->txd.phys, sizeof(desc->lli), +- DMA_TO_DEVICE); +-} +- + /* + * Move a descriptor, including any children, to the free list. + * `desc' must not be on any lists. +@@ -144,8 +148,6 @@ static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) + if (desc) { + struct dw_desc *child; + +- dwc_sync_desc_for_cpu(dwc, desc); +- + spin_lock_irqsave(&dwc->lock, flags); + list_for_each_entry(child, &desc->tx_list, desc_node) + dev_vdbg(chan2dev(&dwc->chan), +@@ -178,9 +180,9 @@ static void dwc_initialize(struct dw_dma_chan *dwc) + cfghi = dws->cfg_hi; + cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK; + } else { +- if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV) ++ if (dwc->direction == DMA_MEM_TO_DEV) + cfghi = DWC_CFGH_DST_PER(dwc->dma_sconfig.slave_id); +- else if (dwc->dma_sconfig.direction == DMA_DEV_TO_MEM) ++ else if (dwc->direction == DMA_DEV_TO_MEM) + cfghi = DWC_CFGH_SRC_PER(dwc->dma_sconfig.slave_id); + } + +@@ -222,7 +224,6 @@ static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) + channel_readl(dwc, CTL_LO)); + } + +- + static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) + { + channel_clear_bit(dw, CH_EN, dwc->mask); +@@ -248,6 +249,9 @@ static inline void dwc_do_single_block(struct dw_dma_chan *dwc, + channel_writel(dwc, CTL_LO, ctllo); + channel_writel(dwc, CTL_HI, desc->lli.ctlhi); + channel_set_bit(dw, CH_EN, dwc->mask); ++ ++ /* Move pointer to next descriptor */ ++ dwc->tx_node_active = dwc->tx_node_active->next; + } + + /* Called with dwc->lock held and bh disabled */ +@@ -278,9 +282,10 @@ static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) + + dwc_initialize(dwc); + +- dwc->tx_list = &first->tx_list; +- dwc->tx_node_active = first->tx_list.next; ++ dwc->residue = first->total_len; ++ dwc->tx_node_active = &first->tx_list; + ++ /* Submit first block */ + dwc_do_single_block(dwc, first); + + return; +@@ -316,8 +321,6 @@ dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, + param = txd->callback_param; + } + +- dwc_sync_desc_for_cpu(dwc, desc); +- + /* async_tx_ack */ + list_for_each_entry(child, &desc->tx_list, desc_node) + async_tx_ack(&child->txd); +@@ -326,29 +329,29 @@ dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, + list_splice_init(&desc->tx_list, &dwc->free_list); + list_move(&desc->desc_node, &dwc->free_list); + +- if (!dwc->chan.private) { ++ if (!is_slave_direction(dwc->direction)) { + struct device *parent = chan2parent(&dwc->chan); + if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { + if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) + dma_unmap_single(parent, desc->lli.dar, +- desc->len, DMA_FROM_DEVICE); ++ desc->total_len, DMA_FROM_DEVICE); + else + dma_unmap_page(parent, desc->lli.dar, +- desc->len, DMA_FROM_DEVICE); ++ desc->total_len, DMA_FROM_DEVICE); + } + if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { + if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) + dma_unmap_single(parent, desc->lli.sar, +- desc->len, DMA_TO_DEVICE); ++ desc->total_len, DMA_TO_DEVICE); + else + dma_unmap_page(parent, desc->lli.sar, +- desc->len, DMA_TO_DEVICE); ++ desc->total_len, DMA_TO_DEVICE); + } + } + + spin_unlock_irqrestore(&dwc->lock, flags); + +- if (callback_required && callback) ++ if (callback) + callback(param); + } + +@@ -383,6 +386,15 @@ static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) + dwc_descriptor_complete(dwc, desc, true); + } + ++/* Returns how many bytes were already received from source */ ++static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) ++{ ++ u32 ctlhi = channel_readl(dwc, CTL_HI); ++ u32 ctllo = channel_readl(dwc, CTL_LO); ++ ++ return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7)); ++} ++ + static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) + { + dma_addr_t llp; +@@ -398,6 +410,39 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) + if (status_xfer & dwc->mask) { + /* Everything we've submitted is done */ + dma_writel(dw, CLEAR.XFER, dwc->mask); ++ ++ if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { ++ struct list_head *head, *active = dwc->tx_node_active; ++ ++ /* ++ * We are inside first active descriptor. ++ * Otherwise something is really wrong. ++ */ ++ desc = dwc_first_active(dwc); ++ ++ head = &desc->tx_list; ++ if (active != head) { ++ /* Update desc to reflect last sent one */ ++ if (active != head->next) ++ desc = to_dw_desc(active->prev); ++ ++ dwc->residue -= desc->len; ++ ++ child = to_dw_desc(active); ++ ++ /* Submit next block */ ++ dwc_do_single_block(dwc, child); ++ ++ spin_unlock_irqrestore(&dwc->lock, flags); ++ return; ++ } ++ ++ /* We are done here */ ++ clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); ++ } ++ ++ dwc->residue = 0; ++ + spin_unlock_irqrestore(&dwc->lock, flags); + + dwc_complete_all(dw, dwc); +@@ -405,6 +450,13 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) + } + + if (list_empty(&dwc->active_list)) { ++ dwc->residue = 0; ++ spin_unlock_irqrestore(&dwc->lock, flags); ++ return; ++ } ++ ++ if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { ++ dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); + spin_unlock_irqrestore(&dwc->lock, flags); + return; + } +@@ -413,6 +465,9 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) + (unsigned long long)llp); + + list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { ++ /* initial residue value */ ++ dwc->residue = desc->total_len; ++ + /* check first descriptors addr */ + if (desc->txd.phys == llp) { + spin_unlock_irqrestore(&dwc->lock, flags); +@@ -422,16 +477,21 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) + /* check first descriptors llp */ + if (desc->lli.llp == llp) { + /* This one is currently in progress */ ++ dwc->residue -= dwc_get_sent(dwc); + spin_unlock_irqrestore(&dwc->lock, flags); + return; + } + +- list_for_each_entry(child, &desc->tx_list, desc_node) ++ dwc->residue -= desc->len; ++ list_for_each_entry(child, &desc->tx_list, desc_node) { + if (child->lli.llp == llp) { + /* Currently in progress */ ++ dwc->residue -= dwc_get_sent(dwc); + spin_unlock_irqrestore(&dwc->lock, flags); + return; + } ++ dwc->residue -= child->len; ++ } + + /* + * No descriptors so far seem to be in progress, i.e. +@@ -457,9 +517,8 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) + + static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) + { +- dev_printk(KERN_CRIT, chan2dev(&dwc->chan), +- " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", +- lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo); ++ dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", ++ lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo); + } + + static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) +@@ -487,16 +546,14 @@ static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) + dwc_dostart(dwc, dwc_first_active(dwc)); + + /* +- * KERN_CRITICAL may seem harsh, but since this only happens ++ * WARN may seem harsh, but since this only happens + * when someone submits a bad physical address in a + * descriptor, we should consider ourselves lucky that the + * controller flagged an error instead of scribbling over + * random memory locations. + */ +- dev_printk(KERN_CRIT, chan2dev(&dwc->chan), +- "Bad descriptor submitted for DMA!\n"); +- dev_printk(KERN_CRIT, chan2dev(&dwc->chan), +- " cookie: %d\n", bad_desc->txd.cookie); ++ dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" ++ " cookie: %d\n", bad_desc->txd.cookie); + dwc_dump_lli(dwc, &bad_desc->lli); + list_for_each_entry(child, &bad_desc->tx_list, desc_node) + dwc_dump_lli(dwc, &child->lli); +@@ -597,36 +654,8 @@ static void dw_dma_tasklet(unsigned long data) + dwc_handle_cyclic(dw, dwc, status_err, status_xfer); + else if (status_err & (1 << i)) + dwc_handle_error(dw, dwc); +- else if (status_xfer & (1 << i)) { +- unsigned long flags; +- +- spin_lock_irqsave(&dwc->lock, flags); +- if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { +- if (dwc->tx_node_active != dwc->tx_list) { +- struct dw_desc *desc = +- list_entry(dwc->tx_node_active, +- struct dw_desc, +- desc_node); +- +- dma_writel(dw, CLEAR.XFER, dwc->mask); +- +- /* move pointer to next descriptor */ +- dwc->tx_node_active = +- dwc->tx_node_active->next; +- +- dwc_do_single_block(dwc, desc); +- +- spin_unlock_irqrestore(&dwc->lock, flags); +- continue; +- } else { +- /* we are done here */ +- clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); +- } +- } +- spin_unlock_irqrestore(&dwc->lock, flags); +- ++ else if (status_xfer & (1 << i)) + dwc_scan_descriptors(dw, dwc); +- } + } + + /* +@@ -639,10 +668,13 @@ static void dw_dma_tasklet(unsigned long data) + static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) + { + struct dw_dma *dw = dev_id; +- u32 status; ++ u32 status = dma_readl(dw, STATUS_INT); + +- dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, +- dma_readl(dw, STATUS_INT)); ++ dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status); ++ ++ /* Check if we have any interrupt from the DMAC */ ++ if (!status) ++ return IRQ_NONE; + + /* + * Just disable the interrupts. We'll turn them back on in the +@@ -708,7 +740,6 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, + size_t len, unsigned long flags) + { + struct dw_dma_chan *dwc = to_dw_dma_chan(chan); +- struct dw_dma_slave *dws = chan->private; + struct dw_desc *desc; + struct dw_desc *first; + struct dw_desc *prev; +@@ -729,8 +760,10 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, + return NULL; + } + +- data_width = min_t(unsigned int, dwc->dw->data_width[dwc_get_sms(dws)], +- dwc->dw->data_width[dwc_get_dms(dws)]); ++ dwc->direction = DMA_MEM_TO_MEM; ++ ++ data_width = min_t(unsigned int, dwc_get_data_width(chan, SRC_MASTER), ++ dwc_get_data_width(chan, DST_MASTER)); + + src_width = dst_width = min_t(unsigned int, data_width, + dwc_fast_fls(src | dest | len)); +@@ -755,32 +788,25 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, + desc->lli.dar = dest + offset; + desc->lli.ctllo = ctllo; + desc->lli.ctlhi = xfer_count; ++ desc->len = xfer_count << src_width; + + if (!first) { + first = desc; + } else { + prev->lli.llp = desc->txd.phys; +- dma_sync_single_for_device(chan2parent(chan), +- prev->txd.phys, sizeof(prev->lli), +- DMA_TO_DEVICE); + list_add_tail(&desc->desc_node, + &first->tx_list); + } + prev = desc; + } + +- + if (flags & DMA_PREP_INTERRUPT) + /* Trigger interrupt after last block */ + prev->lli.ctllo |= DWC_CTLL_INT_EN; + + prev->lli.llp = 0; +- dma_sync_single_for_device(chan2parent(chan), +- prev->txd.phys, sizeof(prev->lli), +- DMA_TO_DEVICE); +- + first->txd.flags = flags; +- first->len = len; ++ first->total_len = len; + + return &first->txd; + +@@ -795,7 +821,6 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, + unsigned long flags, void *context) + { + struct dw_dma_chan *dwc = to_dw_dma_chan(chan); +- struct dw_dma_slave *dws = chan->private; + struct dma_slave_config *sconfig = &dwc->dma_sconfig; + struct dw_desc *prev; + struct dw_desc *first; +@@ -810,9 +835,11 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, + + dev_vdbg(chan2dev(chan), "%s\n", __func__); + +- if (unlikely(!dws || !sg_len)) ++ if (unlikely(!is_slave_direction(direction) || !sg_len)) + return NULL; + ++ dwc->direction = direction; ++ + prev = first = NULL; + + switch (direction) { +@@ -827,7 +854,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, + ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : + DWC_CTLL_FC(DW_DMA_FC_D_M2P); + +- data_width = dwc->dw->data_width[dwc_get_sms(dws)]; ++ data_width = dwc_get_data_width(chan, SRC_MASTER); + + for_each_sg(sgl, sg, sg_len, i) { + struct dw_desc *desc; +@@ -860,15 +887,12 @@ slave_sg_todev_fill_desc: + } + + desc->lli.ctlhi = dlen >> mem_width; ++ desc->len = dlen; + + if (!first) { + first = desc; + } else { + prev->lli.llp = desc->txd.phys; +- dma_sync_single_for_device(chan2parent(chan), +- prev->txd.phys, +- sizeof(prev->lli), +- DMA_TO_DEVICE); + list_add_tail(&desc->desc_node, + &first->tx_list); + } +@@ -890,7 +914,7 @@ slave_sg_todev_fill_desc: + ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : + DWC_CTLL_FC(DW_DMA_FC_D_P2M); + +- data_width = dwc->dw->data_width[dwc_get_dms(dws)]; ++ data_width = dwc_get_data_width(chan, DST_MASTER); + + for_each_sg(sgl, sg, sg_len, i) { + struct dw_desc *desc; +@@ -922,15 +946,12 @@ slave_sg_fromdev_fill_desc: + len = 0; + } + desc->lli.ctlhi = dlen >> reg_width; ++ desc->len = dlen; + + if (!first) { + first = desc; + } else { + prev->lli.llp = desc->txd.phys; +- dma_sync_single_for_device(chan2parent(chan), +- prev->txd.phys, +- sizeof(prev->lli), +- DMA_TO_DEVICE); + list_add_tail(&desc->desc_node, + &first->tx_list); + } +@@ -950,11 +971,7 @@ slave_sg_fromdev_fill_desc: + prev->lli.ctllo |= DWC_CTLL_INT_EN; + + prev->lli.llp = 0; +- dma_sync_single_for_device(chan2parent(chan), +- prev->txd.phys, sizeof(prev->lli), +- DMA_TO_DEVICE); +- +- first->len = total_len; ++ first->total_len = total_len; + + return &first->txd; + +@@ -984,11 +1001,12 @@ set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig) + { + struct dw_dma_chan *dwc = to_dw_dma_chan(chan); + +- /* Check if it is chan is configured for slave transfers */ +- if (!chan->private) ++ /* Check if chan will be configured for slave transfers */ ++ if (!is_slave_direction(sconfig->direction)) + return -EINVAL; + + memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); ++ dwc->direction = sconfig->direction; + + convert_burst(&dwc->dma_sconfig.src_maxburst); + convert_burst(&dwc->dma_sconfig.dst_maxburst); +@@ -996,6 +1014,26 @@ set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig) + return 0; + } + ++static inline void dwc_chan_pause(struct dw_dma_chan *dwc) ++{ ++ u32 cfglo = channel_readl(dwc, CFG_LO); ++ ++ channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); ++ while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY)) ++ cpu_relax(); ++ ++ dwc->paused = true; ++} ++ ++static inline void dwc_chan_resume(struct dw_dma_chan *dwc) ++{ ++ u32 cfglo = channel_readl(dwc, CFG_LO); ++ ++ channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); ++ ++ dwc->paused = false; ++} ++ + static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, + unsigned long arg) + { +@@ -1003,18 +1041,13 @@ static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, + struct dw_dma *dw = to_dw_dma(chan->device); + struct dw_desc *desc, *_desc; + unsigned long flags; +- u32 cfglo; + LIST_HEAD(list); + + if (cmd == DMA_PAUSE) { + spin_lock_irqsave(&dwc->lock, flags); + +- cfglo = channel_readl(dwc, CFG_LO); +- channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); +- while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY)) +- cpu_relax(); ++ dwc_chan_pause(dwc); + +- dwc->paused = true; + spin_unlock_irqrestore(&dwc->lock, flags); + } else if (cmd == DMA_RESUME) { + if (!dwc->paused) +@@ -1022,9 +1055,7 @@ static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, + + spin_lock_irqsave(&dwc->lock, flags); + +- cfglo = channel_readl(dwc, CFG_LO); +- channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); +- dwc->paused = false; ++ dwc_chan_resume(dwc); + + spin_unlock_irqrestore(&dwc->lock, flags); + } else if (cmd == DMA_TERMINATE_ALL) { +@@ -1034,7 +1065,7 @@ static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, + + dwc_chan_disable(dw, dwc); + +- dwc->paused = false; ++ dwc_chan_resume(dwc); + + /* active_list entries will end up before queued entries */ + list_splice_init(&dwc->queue, &list); +@@ -1054,6 +1085,21 @@ static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, + return 0; + } + ++static inline u32 dwc_get_residue(struct dw_dma_chan *dwc) ++{ ++ unsigned long flags; ++ u32 residue; ++ ++ spin_lock_irqsave(&dwc->lock, flags); ++ ++ residue = dwc->residue; ++ if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) ++ residue -= dwc_get_sent(dwc); ++ ++ spin_unlock_irqrestore(&dwc->lock, flags); ++ return residue; ++} ++ + static enum dma_status + dwc_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, +@@ -1070,7 +1116,7 @@ dwc_tx_status(struct dma_chan *chan, + } + + if (ret != DMA_SUCCESS) +- dma_set_residue(txstate, dwc_first_active(dwc)->len); ++ dma_set_residue(txstate, dwc_get_residue(dwc)); + + if (dwc->paused) + return DMA_PAUSED; +@@ -1113,22 +1159,22 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan) + spin_lock_irqsave(&dwc->lock, flags); + i = dwc->descs_allocated; + while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { ++ dma_addr_t phys; ++ + spin_unlock_irqrestore(&dwc->lock, flags); + +- desc = kzalloc(sizeof(struct dw_desc), GFP_KERNEL); +- if (!desc) { +- dev_info(chan2dev(chan), +- "only allocated %d descriptors\n", i); +- spin_lock_irqsave(&dwc->lock, flags); +- break; +- } ++ desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys); ++ if (!desc) ++ goto err_desc_alloc; ++ ++ memset(desc, 0, sizeof(struct dw_desc)); + + INIT_LIST_HEAD(&desc->tx_list); + dma_async_tx_descriptor_init(&desc->txd, chan); + desc->txd.tx_submit = dwc_tx_submit; + desc->txd.flags = DMA_CTRL_ACK; +- desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli, +- sizeof(desc->lli), DMA_TO_DEVICE); ++ desc->txd.phys = phys; ++ + dwc_desc_put(dwc, desc); + + spin_lock_irqsave(&dwc->lock, flags); +@@ -1140,6 +1186,11 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan) + dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); + + return i; ++ ++err_desc_alloc: ++ dev_info(chan2dev(chan), "only allocated %d descriptors\n", i); ++ ++ return i; + } + + static void dwc_free_chan_resources(struct dma_chan *chan) +@@ -1171,14 +1222,56 @@ static void dwc_free_chan_resources(struct dma_chan *chan) + + list_for_each_entry_safe(desc, _desc, &list, desc_node) { + dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); +- dma_unmap_single(chan2parent(chan), desc->txd.phys, +- sizeof(desc->lli), DMA_TO_DEVICE); +- kfree(desc); ++ dma_pool_free(dw->desc_pool, desc, desc->txd.phys); + } + + dev_vdbg(chan2dev(chan), "%s: done\n", __func__); + } + ++bool dw_dma_generic_filter(struct dma_chan *chan, void *param) ++{ ++ struct dw_dma *dw = to_dw_dma(chan->device); ++ static struct dw_dma *last_dw; ++ static char *last_bus_id; ++ int i = -1; ++ ++ /* ++ * dmaengine framework calls this routine for all channels of all dma ++ * controller, until true is returned. If 'param' bus_id is not ++ * registered with a dma controller (dw), then there is no need of ++ * running below function for all channels of dw. ++ * ++ * This block of code does this by saving the parameters of last ++ * failure. If dw and param are same, i.e. trying on same dw with ++ * different channel, return false. ++ */ ++ if ((last_dw == dw) && (last_bus_id == param)) ++ return false; ++ /* ++ * Return true: ++ * - If dw_dma's platform data is not filled with slave info, then all ++ * dma controllers are fine for transfer. ++ * - Or if param is NULL ++ */ ++ if (!dw->sd || !param) ++ return true; ++ ++ while (++i < dw->sd_count) { ++ if (!strcmp(dw->sd[i].bus_id, param)) { ++ chan->private = &dw->sd[i]; ++ last_dw = NULL; ++ last_bus_id = NULL; ++ ++ return true; ++ } ++ } ++ ++ last_dw = dw; ++ last_bus_id = param; ++ return false; ++} ++EXPORT_SYMBOL(dw_dma_generic_filter); ++ + /* --------------------- Cyclic DMA API extensions -------------------- */ + + /** +@@ -1298,6 +1391,11 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, + + retval = ERR_PTR(-EINVAL); + ++ if (unlikely(!is_slave_direction(direction))) ++ goto out_err; ++ ++ dwc->direction = direction; ++ + if (direction == DMA_MEM_TO_DEV) + reg_width = __ffs(sconfig->dst_addr_width); + else +@@ -1312,8 +1410,6 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, + goto out_err; + if (unlikely(buf_addr & ((1 << reg_width) - 1))) + goto out_err; +- if (unlikely(!(direction & (DMA_MEM_TO_DEV | DMA_DEV_TO_MEM)))) +- goto out_err; + + retval = ERR_PTR(-ENOMEM); + +@@ -1371,20 +1467,14 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, + desc->lli.ctlhi = (period_len >> reg_width); + cdesc->desc[i] = desc; + +- if (last) { ++ if (last) + last->lli.llp = desc->txd.phys; +- dma_sync_single_for_device(chan2parent(chan), +- last->txd.phys, sizeof(last->lli), +- DMA_TO_DEVICE); +- } + + last = desc; + } + + /* lets make a cyclic list */ + last->lli.llp = cdesc->desc[0]->txd.phys; +- dma_sync_single_for_device(chan2parent(chan), last->txd.phys, +- sizeof(last->lli), DMA_TO_DEVICE); + + dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu " + "period %zu periods %d\n", (unsigned long long)buf_addr, +@@ -1462,6 +1552,91 @@ static void dw_dma_off(struct dw_dma *dw) + dw->chan[i].initialized = false; + } + ++#ifdef CONFIG_OF ++static struct dw_dma_platform_data * ++dw_dma_parse_dt(struct platform_device *pdev) ++{ ++ struct device_node *sn, *cn, *np = pdev->dev.of_node; ++ struct dw_dma_platform_data *pdata; ++ struct dw_dma_slave *sd; ++ u32 tmp, arr[4]; ++ ++ if (!np) { ++ dev_err(&pdev->dev, "Missing DT data\n"); ++ return NULL; ++ } ++ ++ pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); ++ if (!pdata) ++ return NULL; ++ ++ if (of_property_read_u32(np, "nr_channels", &pdata->nr_channels)) ++ return NULL; ++ ++ if (of_property_read_bool(np, "is_private")) ++ pdata->is_private = true; ++ ++ if (!of_property_read_u32(np, "chan_allocation_order", &tmp)) ++ pdata->chan_allocation_order = (unsigned char)tmp; ++ ++ if (!of_property_read_u32(np, "chan_priority", &tmp)) ++ pdata->chan_priority = tmp; ++ ++ if (!of_property_read_u32(np, "block_size", &tmp)) ++ pdata->block_size = tmp; ++ ++ if (!of_property_read_u32(np, "nr_masters", &tmp)) { ++ if (tmp > 4) ++ return NULL; ++ ++ pdata->nr_masters = tmp; ++ } ++ ++ if (!of_property_read_u32_array(np, "data_width", arr, ++ pdata->nr_masters)) ++ for (tmp = 0; tmp < pdata->nr_masters; tmp++) ++ pdata->data_width[tmp] = arr[tmp]; ++ ++ /* parse slave data */ ++ sn = of_find_node_by_name(np, "slave_info"); ++ if (!sn) ++ return pdata; ++ ++ /* calculate number of slaves */ ++ tmp = of_get_child_count(sn); ++ if (!tmp) ++ return NULL; ++ ++ sd = devm_kzalloc(&pdev->dev, sizeof(*sd) * tmp, GFP_KERNEL); ++ if (!sd) ++ return NULL; ++ ++ pdata->sd = sd; ++ pdata->sd_count = tmp; ++ ++ for_each_child_of_node(sn, cn) { ++ sd->dma_dev = &pdev->dev; ++ of_property_read_string(cn, "bus_id", &sd->bus_id); ++ of_property_read_u32(cn, "cfg_hi", &sd->cfg_hi); ++ of_property_read_u32(cn, "cfg_lo", &sd->cfg_lo); ++ if (!of_property_read_u32(cn, "src_master", &tmp)) ++ sd->src_master = tmp; ++ ++ if (!of_property_read_u32(cn, "dst_master", &tmp)) ++ sd->dst_master = tmp; ++ sd++; ++ } ++ ++ return pdata; ++} ++#else ++static inline struct dw_dma_platform_data * ++dw_dma_parse_dt(struct platform_device *pdev) ++{ ++ return NULL; ++} ++#endif ++ + static int dw_probe(struct platform_device *pdev) + { + struct dw_dma_platform_data *pdata; +@@ -1477,10 +1652,6 @@ static int dw_probe(struct platform_device *pdev) + int err; + int i; + +- pdata = dev_get_platdata(&pdev->dev); +- if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) +- return -EINVAL; +- + io = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!io) + return -EINVAL; +@@ -1493,9 +1664,33 @@ static int dw_probe(struct platform_device *pdev) + if (!regs) + return -EBUSY; + ++ /* Apply default dma_mask if needed */ ++ if (!pdev->dev.dma_mask) { ++ pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; ++ pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); ++ } ++ + dw_params = dma_read_byaddr(regs, DW_PARAMS); + autocfg = dw_params >> DW_PARAMS_EN & 0x1; + ++ dev_dbg(&pdev->dev, "DW_PARAMS: 0x%08x\n", dw_params); ++ ++ pdata = dev_get_platdata(&pdev->dev); ++ if (!pdata) ++ pdata = dw_dma_parse_dt(pdev); ++ ++ if (!pdata && autocfg) { ++ pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); ++ if (!pdata) ++ return -ENOMEM; ++ ++ /* Fill platform data with the default values */ ++ pdata->is_private = true; ++ pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; ++ pdata->chan_priority = CHAN_PRIORITY_ASCENDING; ++ } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) ++ return -EINVAL; ++ + if (autocfg) + nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1; + else +@@ -1512,6 +1707,8 @@ static int dw_probe(struct platform_device *pdev) + clk_prepare_enable(dw->clk); + + dw->regs = regs; ++ dw->sd = pdata->sd; ++ dw->sd_count = pdata->sd_count; + + /* get hardware configuration parameters */ + if (autocfg) { +@@ -1536,13 +1733,21 @@ static int dw_probe(struct platform_device *pdev) + /* disable BLOCK interrupts as well */ + channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); + +- err = devm_request_irq(&pdev->dev, irq, dw_dma_interrupt, 0, ++ err = devm_request_irq(&pdev->dev, irq, dw_dma_interrupt, IRQF_SHARED, + "dw_dmac", dw); + if (err) + return err; + + platform_set_drvdata(pdev, dw); + ++ /* create a pool of consistent memory blocks for hardware descriptors */ ++ dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", &pdev->dev, ++ sizeof(struct dw_desc), 4, 0); ++ if (!dw->desc_pool) { ++ dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); ++ return -ENOMEM; ++ } ++ + tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); + + INIT_LIST_HEAD(&dw->dma.channels); +@@ -1574,7 +1779,7 @@ static int dw_probe(struct platform_device *pdev) + + channel_clear_bit(dw, CH_EN, dwc->mask); + +- dwc->dw = dw; ++ dwc->direction = DMA_TRANS_NONE; + + /* hardware configuration */ + if (autocfg) { +@@ -1583,6 +1788,9 @@ static int dw_probe(struct platform_device *pdev) + dwc_params = dma_read_byaddr(regs + r * sizeof(u32), + DWC_PARAMS); + ++ dev_dbg(&pdev->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, ++ dwc_params); ++ + /* Decode maximum block size for given channel. The + * stored 4 bit value represents blocks from 0x00 for 3 + * up to 0x0a for 4095. */ +@@ -1626,8 +1834,8 @@ static int dw_probe(struct platform_device *pdev) + + dma_writel(dw, CFG, DW_CFG_DMA_EN); + +- printk(KERN_INFO "%s: DesignWare DMA Controller, %d channels\n", +- dev_name(&pdev->dev), nr_channels); ++ dev_info(&pdev->dev, "DesignWare DMA Controller, %d channels\n", ++ nr_channels); + + dma_async_device_register(&dw->dma); + +@@ -1657,7 +1865,7 @@ static void dw_shutdown(struct platform_device *pdev) + { + struct dw_dma *dw = platform_get_drvdata(pdev); + +- dw_dma_off(platform_get_drvdata(pdev)); ++ dw_dma_off(dw); + clk_disable_unprepare(dw->clk); + } + +@@ -1666,7 +1874,7 @@ static int dw_suspend_noirq(struct device *dev) + struct platform_device *pdev = to_platform_device(dev); + struct dw_dma *dw = platform_get_drvdata(pdev); + +- dw_dma_off(platform_get_drvdata(pdev)); ++ dw_dma_off(dw); + clk_disable_unprepare(dw->clk); + + return 0; +@@ -1679,6 +1887,7 @@ static int dw_resume_noirq(struct device *dev) + + clk_prepare_enable(dw->clk); + dma_writel(dw, CFG, DW_CFG_DMA_EN); ++ + return 0; + } + +@@ -1699,7 +1908,15 @@ static const struct of_device_id dw_dma_id_table[] = { + MODULE_DEVICE_TABLE(of, dw_dma_id_table); + #endif + ++static const struct platform_device_id dw_dma_ids[] = { ++ { "INTL9C60", 0 }, ++ { "80860F06", 0 }, ++ { "80860F40", 0 }, ++ { } ++}; ++ + static struct platform_driver dw_driver = { ++ .probe = dw_probe, + .remove = dw_remove, + .shutdown = dw_shutdown, + .driver = { +@@ -1707,11 +1924,12 @@ static struct platform_driver dw_driver = { + .pm = &dw_dev_pm_ops, + .of_match_table = of_match_ptr(dw_dma_id_table), + }, ++ .id_table = dw_dma_ids, + }; + + static int __init dw_init(void) + { +- return platform_driver_probe(&dw_driver, dw_probe); ++ return platform_driver_register(&dw_driver); + } + subsys_initcall(dw_init); + +diff --git a/drivers/dma/dw_dmac_pci.c b/drivers/dma/dw_dmac_pci.c +new file mode 100644 +index 0000000..ecdacaf +--- /dev/null ++++ b/drivers/dma/dw_dmac_pci.c +@@ -0,0 +1,164 @@ ++/* ++ * PCI driver for the Synopsys DesignWare DMA Controller ++ * ++ * Copyright (C) 2012 Intel Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include <linux/module.h> ++#include <linux/idr.h> ++#include <linux/pci.h> ++#include <linux/platform_device.h> ++#include <linux/dw_dmac.h> ++ ++static struct dw_dma_platform_data dw_pci_pdata = { ++ .is_private = 1, ++ .chan_allocation_order = CHAN_ALLOCATION_ASCENDING, ++ .chan_priority = CHAN_PRIORITY_ASCENDING, ++}; ++ ++static DEFINE_IDA(dw_pci_ida); ++ ++static int dw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pid) ++{ ++ struct platform_device *pd; ++ struct resource r[2]; ++ struct dw_dma_platform_data *driver = (void *)pid->driver_data; ++ int id, ret; ++ ++ id = ida_simple_get(&dw_pci_ida, 0, 0, GFP_KERNEL); ++ if (id < 0) ++ return id; ++ ++ ret = pci_enable_device(pdev); ++ if (ret) ++ goto put_id; ++ ++ pci_set_power_state(pdev, PCI_D0); ++ pci_set_master(pdev); ++ pci_try_set_mwi(pdev); ++ ++ ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); ++ if (ret) ++ goto err0; ++ ++ ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); ++ if (ret) ++ goto err0; ++ ++ pd = platform_device_alloc("dw_dmac", id); ++ if (!pd) { ++ dev_err(&pdev->dev, "can't allocate dw_dmac platform device\n"); ++ ret = -ENOMEM; ++ goto err0; ++ } ++ ++ memset(r, 0, sizeof(r)); ++ ++ r[0].start = pci_resource_start(pdev, 0); ++ r[0].end = pci_resource_end(pdev, 0); ++ r[0].flags = IORESOURCE_MEM; ++ ++ r[1].start = pdev->irq; ++ r[1].flags = IORESOURCE_IRQ; ++ ++ ret = platform_device_add_resources(pd, r, ARRAY_SIZE(r)); ++ if (ret) { ++ dev_err(&pdev->dev, "can't add resources to platform device\n"); ++ goto err1; ++ } ++ ++ ret = platform_device_add_data(pd, driver, sizeof(*driver)); ++ if (ret) ++ goto err1; ++ ++ dma_set_coherent_mask(&pd->dev, pdev->dev.coherent_dma_mask); ++ pd->dev.dma_mask = pdev->dev.dma_mask; ++ pd->dev.dma_parms = pdev->dev.dma_parms; ++ pd->dev.parent = &pdev->dev; ++ ++ pci_set_drvdata(pdev, pd); ++ ++ ret = platform_device_add(pd); ++ if (ret) { ++ dev_err(&pdev->dev, "platform_device_add failed\n"); ++ goto err1; ++ } ++ ++ return 0; ++ ++err1: ++ platform_device_put(pd); ++err0: ++ pci_disable_device(pdev); ++put_id: ++ ida_simple_remove(&dw_pci_ida, id); ++ return ret; ++} ++ ++static void dw_pci_remove(struct pci_dev *pdev) ++{ ++ struct platform_device *pd = pci_get_drvdata(pdev); ++ ++ platform_device_unregister(pd); ++ ida_simple_remove(&dw_pci_ida, pd->id); ++ pci_set_drvdata(pdev, NULL); ++ pci_disable_device(pdev); ++} ++ ++static int dw_dmac_pci_resume(struct device *dev) ++{ ++ struct pci_dev *pci = to_pci_dev(dev); ++ int ret; ++ ++ pci_set_power_state(pci, PCI_D0); ++ pci_restore_state(pci); ++ ret = pci_enable_device(pci); ++ if (ret) ++ return ret; ++ ++ return 0; ++}; ++ ++static int dw_dmac_pci_suspend(struct device *dev) ++{ ++ struct pci_dev *pci = to_pci_dev(dev); ++ ++ pci_save_state(pci); ++ pci_disable_device(pci); ++ pci_set_power_state(pci, PCI_D3hot); ++ return 0; ++}; ++ ++static const struct dev_pm_ops dw_dma_pm_ops = { ++ .resume_noirq = dw_dmac_pci_resume, ++ .suspend_noirq = dw_dmac_pci_suspend, ++}; ++ ++static DEFINE_PCI_DEVICE_TABLE(dw_pci_id_table) = { ++ { PCI_VDEVICE(INTEL, 0x0827), (kernel_ulong_t)&dw_pci_pdata }, ++ { PCI_VDEVICE(INTEL, 0x0830), (kernel_ulong_t)&dw_pci_pdata }, ++ { PCI_VDEVICE(INTEL, 0x0f06), (kernel_ulong_t)&dw_pci_pdata }, ++ { 0, } ++}; ++MODULE_DEVICE_TABLE(pci, dw_pci_id_table); ++ ++static struct pci_driver dw_pci_driver = { ++ .name = "dw_dmac_pci", ++ .id_table = dw_pci_id_table, ++ .probe = dw_pci_probe, ++ .remove = dw_pci_remove, ++ .driver = { ++ .pm = &dw_dma_pm_ops, ++ }, ++}; ++ ++module_pci_driver(dw_pci_driver); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("DesignWare DMAC PCI driver"); ++MODULE_AUTHOR("Heikki Krogerus <[email protected]>"); ++MODULE_AUTHOR("Andy Shevchenko <[email protected]>"); +diff --git a/drivers/dma/dw_dmac_regs.h b/drivers/dma/dw_dmac_regs.h +index 8896559..88dd8eb 100644 +--- a/drivers/dma/dw_dmac_regs.h ++++ b/drivers/dma/dw_dmac_regs.h +@@ -9,6 +9,7 @@ + * published by the Free Software Foundation. + */ + ++#include <linux/dmaengine.h> + #include <linux/dw_dmac.h> + + #define DW_DMA_MAX_NR_CHANNELS 8 +@@ -184,15 +185,15 @@ enum dw_dmac_flags { + }; + + struct dw_dma_chan { +- struct dma_chan chan; +- void __iomem *ch_regs; +- u8 mask; +- u8 priority; +- bool paused; +- bool initialized; ++ struct dma_chan chan; ++ void __iomem *ch_regs; ++ u8 mask; ++ u8 priority; ++ enum dma_transfer_direction direction; ++ bool paused; ++ bool initialized; + + /* software emulation of the LLP transfers */ +- struct list_head *tx_list; + struct list_head *tx_node_active; + + spinlock_t lock; +@@ -202,6 +203,7 @@ struct dw_dma_chan { + struct list_head active_list; + struct list_head queue; + struct list_head free_list; ++ u32 residue; + struct dw_cyclic_desc *cdesc; + + unsigned int descs_allocated; +@@ -212,9 +214,6 @@ struct dw_dma_chan { + + /* configuration passed via DMA_SLAVE_CONFIG */ + struct dma_slave_config dma_sconfig; +- +- /* backlink to dw_dma */ +- struct dw_dma *dw; + }; + + static inline struct dw_dma_chan_regs __iomem * +@@ -236,9 +235,14 @@ static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan) + struct dw_dma { + struct dma_device dma; + void __iomem *regs; ++ struct dma_pool *desc_pool; + struct tasklet_struct tasklet; + struct clk *clk; + ++ /* slave information */ ++ struct dw_dma_slave *sd; ++ unsigned int sd_count; ++ + u8 all_chan_mask; + + /* hardware configuration */ +@@ -293,8 +297,11 @@ struct dw_desc { + struct list_head tx_list; + struct dma_async_tx_descriptor txd; + size_t len; ++ size_t total_len; + }; + ++#define to_dw_desc(h) list_entry(h, struct dw_desc, desc_node) ++ + static inline struct dw_desc * + txd_to_dw_desc(struct dma_async_tx_descriptor *txd) + { +diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h +index d3201e4..2f60fea 100644 +--- a/include/linux/dmaengine.h ++++ b/include/linux/dmaengine.h +@@ -618,6 +618,11 @@ static inline int dmaengine_slave_config(struct dma_chan *chan, + (unsigned long)config); + } + ++static inline bool is_slave_direction(enum dma_transfer_direction direction) ++{ ++ return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM); ++} ++ + static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single( + struct dma_chan *chan, dma_addr_t buf, size_t len, + enum dma_transfer_direction dir, unsigned long flags) +diff --git a/include/linux/dw_dmac.h b/include/linux/dw_dmac.h +index e1c8c9e..6da35bb 100644 +--- a/include/linux/dw_dmac.h ++++ b/include/linux/dw_dmac.h +@@ -15,6 +15,26 @@ + #include <linux/dmaengine.h> + + /** ++ * struct dw_dma_slave - Controller-specific information about a slave ++ * ++ * @dma_dev: required DMA master device. Depricated. ++ * @bus_id: name of this device channel, not just a device name since ++ * devices may have more than one channel e.g. "foo_tx" ++ * @cfg_hi: Platform-specific initializer for the CFG_HI register ++ * @cfg_lo: Platform-specific initializer for the CFG_LO register ++ * @src_master: src master for transfers on allocated channel. ++ * @dst_master: dest master for transfers on allocated channel. ++ */ ++struct dw_dma_slave { ++ struct device *dma_dev; ++ const char *bus_id; ++ u32 cfg_hi; ++ u32 cfg_lo; ++ u8 src_master; ++ u8 dst_master; ++}; ++ ++/** + * struct dw_dma_platform_data - Controller configuration parameters + * @nr_channels: Number of channels supported by hardware (max 8) + * @is_private: The device channels should be marked as private and not for +@@ -23,6 +43,8 @@ + * @nr_masters: Number of AHB masters supported by the controller + * @data_width: Maximum data width supported by hardware per AHB master + * (0 - 8bits, 1 - 16bits, ..., 5 - 256bits) ++ * @sd: slave specific data. Used for configuring channels ++ * @sd_count: count of slave data structures passed. + */ + struct dw_dma_platform_data { + unsigned int nr_channels; +@@ -36,6 +58,9 @@ struct dw_dma_platform_data { + unsigned short block_size; + unsigned char nr_masters; + unsigned char data_width[4]; ++ ++ struct dw_dma_slave *sd; ++ unsigned int sd_count; + }; + + /* bursts size */ +@@ -50,23 +75,6 @@ enum dw_dma_msize { + DW_DMA_MSIZE_256, + }; + +-/** +- * struct dw_dma_slave - Controller-specific information about a slave +- * +- * @dma_dev: required DMA master device +- * @cfg_hi: Platform-specific initializer for the CFG_HI register +- * @cfg_lo: Platform-specific initializer for the CFG_LO register +- * @src_master: src master for transfers on allocated channel. +- * @dst_master: dest master for transfers on allocated channel. +- */ +-struct dw_dma_slave { +- struct device *dma_dev; +- u32 cfg_hi; +- u32 cfg_lo; +- u8 src_master; +- u8 dst_master; +-}; +- + /* Platform-configurable bits in CFG_HI */ + #define DWC_CFGH_FCMODE (1 << 0) + #define DWC_CFGH_FIFO_MODE (1 << 1) +@@ -104,5 +112,6 @@ void dw_dma_cyclic_stop(struct dma_chan *chan); + dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan); + + dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan); ++bool dw_dma_generic_filter(struct dma_chan *chan, void *param); + + #endif /* DW_DMAC_H */ +-- +1.7.10.4 + -- 1.7.10.4 _______________________________________________ linux-yocto mailing list [email protected] https://lists.yoctoproject.org/listinfo/linux-yocto
