On 15-08-31 07:34 AM, Kevin Hao wrote:
Even the octeon plus has the support of the 'saa' instruction, but we don't have a way to distinguish between octeon and octeon plus at compile time and pass "-march=octeon" to all the predecessor of octeon2. So it will cause the following error when trying to assemble the "saa" instruction with option "-march=octeon": {standard input}: Assembler messages: {standard input}:360: Error: Unrecognized opcode `saa $2,($4)' scripts/Makefile.build:308: recipe for target 'arch/mips/cavium-octeon/executive/cvmx-lap.o' failedForcing to use the "ll/sc" for the atomic ops for all the predecessor of octeon2 to fix this issue.
Thanks Kevin, My test builds have passed, so I've queued this and will send it out shortly. Bruce
Signed-off-by: Kevin Hao <[email protected]> --- arch/mips/include/asm/octeon/cvmx-atomic.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/mips/include/asm/octeon/cvmx-atomic.h b/arch/mips/include/asm/octeon/cvmx-atomic.h index f4bfb7598634..b2b06438c24f 100644 --- a/arch/mips/include/asm/octeon/cvmx-atomic.h +++ b/arch/mips/include/asm/octeon/cvmx-atomic.h @@ -79,7 +79,7 @@ static inline void cvmx_atomic_add32_nosync(int32_t * ptr, int32_t incr) :"memory"); } #else - if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) { + { uint32_t tmp; __asm__ __volatile__(".set noreorder \n" @@ -89,10 +89,6 @@ static inline void cvmx_atomic_add32_nosync(int32_t * ptr, int32_t incr) " beqz %[tmp], 1b \n" " nop \n" ".set reorder \n":[val] "+m"(*ptr),[tmp] "=&r"(tmp) :[inc] "r"(incr) :"memory"); - } else { - __asm__ __volatile__(" saa %[inc], (%[base]) \n":"+m"(*ptr) - :[inc] "r"(incr),[base] "r"(ptr) - :"memory"); } #endif }
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