From: John Jacques <[email protected]>
Signed-off-by: John Jacques <[email protected]>
---
arch/arm64/boot/dts/intel/Makefile | 2 +-
arch/arm64/boot/dts/intel/axc6704-cpus.dtsi | 310 +++++++++++++++++++++++++++-
arch/arm64/boot/dts/intel/axc6704-waco.dts | 259 +++++++++++++++++++++++
3 files changed, 566 insertions(+), 5 deletions(-)
create mode 100644 arch/arm64/boot/dts/intel/axc6704-waco.dts
diff --git a/arch/arm64/boot/dts/intel/Makefile
b/arch/arm64/boot/dts/intel/Makefile
index da244aa..6e7cc1c 100644
--- a/arch/arm64/boot/dts/intel/Makefile
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -4,7 +4,7 @@ dtb-$(CONFIG_ARCH_AXXIA) += \
axm5616-victoria.dtb \
axc6704-sim.dtb axc6716-sim.dtb axc6732-sim.dtb \
axc6704-emu.dtb axc6712-emu.dtb \
- axc6732-waco.dtb
+ axc6704-waco.dtb axc6732-waco.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/intel/axc6704-cpus.dtsi
b/arch/arm64/boot/dts/intel/axc6704-cpus.dtsi
index 9a67423..0b422c3 100644
--- a/arch/arm64/boot/dts/intel/axc6704-cpus.dtsi
+++ b/arch/arm64/boot/dts/intel/axc6704-cpus.dtsi
@@ -14,32 +14,334 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x00>;
enable-method = "psci";
};
- cpu@1 {
+ CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x01>;
enable-method = "psci";
};
- cpu@2 {
+ CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x02>;
enable-method = "psci";
};
- cpu@3 {
+ CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x03>;
enable-method = "psci";
};
};
+
+
+ mainfunnel@8008007000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x80 0x08007000 0 0x1000>;
+
+ clocks = <&clk_per 0>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ main_funnel_out_port: endpoint {
+ remote-endpoint = <&main_etf_in_port>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ main_funnel_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint =
<&mid_funnel0_out_port>;
+ };
+ };
+/*
+
+ port@2 {
+ reg = <1>;
+ main_funnel_in_port1: endpoint {
+ slave-mode;
+ remote-endpoint =
<&mid_funnel1_out_port>;
+ };
+ };
+
+ port@3 {
+ reg = <2>;
+ main_funnel_in_port2: endpoint {
+ slave-mode;
+ remote-endpoint =
<&mid_funnel2_out_port>;
+ };
+ };
+
+
+ port@4 {
+ reg = <3>;
+ main_funnel_in_port3: endpoint {
+ slave-mode;
+ remote-endpoint =
<&mid_funnel3_out_port>;
+ };
+
+ };
+
+ port@5 {
+ reg = <4>;
+ main_funnel_in_port4: endpoint {
+ slave_mode;
+ remote-endpoint =
<&mid_funnel4_out_port>;
+ };
+ };
+*/
+ };
+ };
+
+
+ etr@8008046000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x80 0x08046000 0 0x1000>;
+
+ clocks = <&clk_per 0>;
+ clock-names = "apb_pclk";
+ port {
+ etr_in_port: endpoint {
+ slave-mode;
+ remote-endpoint = <&main_etf_out_port>;
+ };
+ };
+ };
+
+ etm0: etm@8008C40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x80 0x08C40000 0 0x1000>;
+
+ clocks = <&clk_per 0>;
+ clock-names = "apb_pclk";
+ cpu = <&CPU0>;
+ port {
+ cluster0_etm0_out_port: endpoint {
+ remote-endpoint = <&cluster0_funnel_in_port0>;
+ };
+ };
+ };
+
+
+ etm1: etm@8008D40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x80 0x08D40000 0 0x1000>;
+
+ clocks = <&clk_per 0>;
+ clock-names = "apb_pclk";
+ cpu = <&CPU1>;
+ port {
+ cluster0_etm1_out_port: endpoint {
+ remote-endpoint = <&cluster0_funnel_in_port1>;
+ };
+ };
+ };
+
+ etm2: etm@8008E40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x80 0x08E40000 0 0x1000>;
+
+ clocks = <&clk_per 0>;
+ clock-names = "apb_pclk";
+ cpu = <&CPU2>;
+ port {
+ cluster0_etm2_out_port: endpoint {
+ remote-endpoint = <&cluster0_funnel_in_port2>;
+ };
+ };
+ };
+
+
+ etm3: etm@8008F40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x80 0x08F40000 0 0x1000>;
+
+ clocks = <&clk_per 0>;
+ clock-names = "apb_pclk";
+ cpu = <&CPU3>;
+ port {
+ cluster0_etm3_out_port: endpoint {
+ remote-endpoint = <&cluster0_funnel_in_port3>;
+ };
+ };
+ };
+
+
+ etf@8008009000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x80 0x08009000 0 0x1000>;
+
+ clocks = <&clk_per 0>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* input port */
+ port@0 {
+ reg = <0>;
+ cluster0_etf_in_port: endpoint {
+ slave-mode;
+ remote-endpoint =
<&cluster0_funnel_out_port>;
+ };
+ };
+
+ /* output port */
+ port@1 {
+ reg = <0>;
+ cluster0_etf_out_port: endpoint {
+ remote-endpoint =
<&mid_funnel0_in_port0>;
+ };
+ };
+ };
+ };
+
+
+ funnel@8008810000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x80 0x08810000 0 0x1000>;
+
+ clocks = <&clk_per 0>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ cluster0_funnel_out_port: endpoint {
+ remote-endpoint =
<&cluster0_etf_in_port>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ cluster0_funnel_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint =
<&cluster0_etm0_out_port>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ cluster0_funnel_in_port1: endpoint {
+ slave-mode;
+ remote-endpoint =
<&cluster0_etm1_out_port>;
+ };
+ };
+
+ port@3 {
+ reg = <2>;
+ cluster0_funnel_in_port2: endpoint {
+ slave-mode;
+ remote-endpoint =
<&cluster0_etm2_out_port>;
+ };
+ };
+
+ port@4 {
+ reg = <3>;
+ cluster0_funnel_in_port3: endpoint {
+ slave-mode;
+ remote-endpoint =
<&cluster0_etm3_out_port>;
+ };
+ };
+ };
+ };
+
+
+ mainetf@8008045000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x80 0x08045000 0 0x1000>;
+
+ clocks = <&clk_per 0>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* input port */
+ port@0 {
+ reg = <0>;
+ main_etf_in_port: endpoint {
+ slave-mode;
+ remote-endpoint =
<&main_funnel_out_port>;
+ };
+ };
+
+ /* output port */
+ port@1 {
+ reg = <0>;
+ main_etf_out_port: endpoint {
+ remote-endpoint = <&etr_in_port>;
+ };
+ };
+ };
+ };
+
+
+ funnel@8008002000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x80 0x08002000 0 0x1000>;
+
+ clocks = <&clk_per 0>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mid_funnel0_out_port: endpoint {
+ remote-endpoint =
<&main_funnel_in_port0>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ mid_funnel0_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint =
<&cluster0_etf_out_port>;
+ };
+ };
+/*
+ port@2 {
+ reg = <1>;
+ mid_funnel0_in_port1: endpoint {
+ slave-mode;
+ remote-endpoint =
<&cluster1_etf_out_port>;
+ };
+ };
+
+ port@3 {
+ reg = <2>;
+ mid_funnel0_in_port2: endpoint {
+ slave-mode;
+ remote-endpoint =
<&cluster2_etf_out_port>;
+ };
+ };
+
+ port@4 {
+ reg = <3>;
+ mid_funnel0_in_port3: endpoint {
+ slave-mode;
+ remote-endpoint =
<&cluster3_etf_out_port>;
+ };
+ };
+*/
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/intel/axc6704-waco.dts
b/arch/arm64/boot/dts/intel/axc6704-waco.dts
new file mode 100644
index 0000000..c651dad
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/axc6704-waco.dts
@@ -0,0 +1,259 @@
+/*
+ * arch/arm64/boot/dts/intel/axc6704-waco.dts
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+
+#include "axc67xx.dtsi"
+#include "axc6704-cpus.dtsi"
+
+/ {
+ model = "Lionfish";
+ compatible = "lsi,axc6732";
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x00000000 0 0x40000000>;
+ };
+
+ soc {
+ };
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&nemac {
+ status = "okay";
+ phy-handle = <&phy0>;
+};
+
+&mdio0 {
+ status = "okay";
+ lsi,mdio-clk-offset = <0x1c>;
+ lsi,mdio-clk-period = <0xf0>;
+ max-speed = <10>;
+
+ phy0: ethernet-phy@3 {
+ reg = <0x7>;
+ };
+};
+
+&mdio1 {
+ status = "okay";
+ lsi,mdio-clk-offset = <0x1c>;
+ lsi,mdio-clk-period = <0xf0>;
+ max-speed = <10>;
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "s25fl016k";
+ reg = <0>;
+ spi-max-frequency = <5000000>;
+ pl022,com-mode = <1>;
+
+ partition@0 {
+ label = "spl-0";
+ reg = <0x0 0x40000>;
+ };
+ partition@40000 {
+ label = "spl-1";
+ reg = <0x40000 0x40000>;
+ };
+ partition@80000 {
+ label = "parameters-0";
+ reg = <0x80000 0x10000>;
+ };
+ partition@90000 {
+ label = "parameters-1";
+ reg = <0x90000 0x10000>;
+ };
+ partition@a0000 {
+ label = "env-0";
+ reg = <0xa0000 0x10000>;
+ };
+ partition@b0000 {
+ label = "env-1";
+ reg = <0xb0000 0x10000>;
+ };
+ partition@100000 {
+ label = "u-boot-0";
+ reg = <0x100000 0x200000>;
+ };
+ partition@300000 {
+ label = "u-boot-1";
+ reg = <0x300000 0x200000>;
+ };
+ };
+
+ flash@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "s25fl016k";
+ reg = <1>;
+ spi-max-frequency = <5000000>;
+ pl022,com-mode = <1>;
+
+ partition@0 {
+ label = "spl-0";
+ reg = <0x0 0x40000>;
+ };
+ partition@40000 {
+ label = "spl-1";
+ reg = <0x40000 0x40000>;
+ };
+ partition@80000 {
+ label = "parameters-0";
+ reg = <0x80000 0x10000>;
+ };
+ partition@90000 {
+ label = "parameters-1";
+ reg = <0x90000 0x10000>;
+ };
+ partition@a0000 {
+ label = "env-0";
+ reg = <0xa0000 0x10000>;
+ };
+ partition@b0000 {
+ label = "env-1";
+ reg = <0xb0000 0x10000>;
+ };
+ partition@100000 {
+ label = "u-boot-0";
+ reg = <0x100000 0x200000>;
+ };
+ partition@300000 {
+ label = "u-boot-1";
+ reg = <0x300000 0x200000>;
+ };
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&i2c8 {
+ status = "okay";
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&gpio3 {
+ status = "okay";
+};
+
+&gpio4 {
+ status = "okay";
+};
+
+&gpio5 {
+ status = "okay";
+};
+
+&gpio6 {
+ status = "okay";
+};
+
+&gpio7 {
+ status = "okay";
+};
+
+&gpio8 {
+ status = "okay";
+};
+
+&gpio9 {
+ status = "okay";
+};
+
+&gpio10 {
+ status = "okay";
+};
+
+&gpio11 {
+ status = "okay";
+};
+
+&mtc {
+ status = "okay";
+};
+
+&trng {
+ status = "okay";
+};
--
2.7.4
--
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