On 2018年01月10日 11:11, Bruce Ashfield wrote:
On 2018-01-09 9:07 PM, qwang2 wrote:
Hi Bruce,

This commit is based on the patches at https://www.mail-archive.com/[email protected]/msg06131.html.

It seems that those patches hasn't been merged, would you please help to check it?

Send them all in a completes series.
Hi Bruce,

I made all these patches in a completes series, and they are at the git-tree as below.

Thanks,
Quanyang

The following changes since commit 4226b065fca4f630901d99b99d18c395ae3866fb:

ipv4: net namespace does not inherit network configurations (2017-12-05 17:17:05 -0500)

are available in the git repository at:

  https://github.com/wangquanyang/linux-yocto-4.12.git standard/base

for you to fetch changes up to 1d07c0cde181b7746c6091dc276ff6a205d5ca23:

x86/intel_rdt: Turn off most RDT features on Skylake (2018-01-10 13:13:22 +0800)

----------------------------------------------------------------
Alexei Starovoitov (1):
      perf, bpf: Add BPF support to all perf_event types

Arnaldo Carvalho de Melo (5):
      tools: Adopt __noreturn from kernel sources
      perf event-parse: Use pr_warning()
      tools: Adopt __printf from kernel sources
      perf tools: Remove warning()
      perf test: Add 'struct test *' to the test functions

Colin Ian King (2):
      x86/intel_rdt: Remove redundant ternary operator on return
      x86/intel_rdt/cqm: Make integer rmid_limbo_count static

Fenghua Yu (1):
x86/intel_rdt: Show bitmask of shareable resource with other executing units

Jithu Joseph (1):
      x86/intel_rdt: Remove redundant assignment

Reinette Chatre (2):
      x86/intel_rdt: Mark rdt_root and closid_alloc as static
x86/intel_rdt: Initialize bitmask of shareable resource if CDP enabled

Sebastian Andrzej Siewior (1):
      perf/x86/intel/cqm: Use cpuhp_setup_state_cpuslocked()

Tony Luck (10):
      x86/intel_rdt: Simplify info and base file lists
      x86/intel_rdt/mbm: Basic counting of MBM events (total and local)
      x86/intel_rdt: Add framework for better RDT UI diagnostics
      x86/intel_rdt: Add diagnostics when writing the schemata file
      x86/intel_rdt: Add diagnostics when writing the tasks file
      x86/intel_rdt: Add diagnostics when writing the cpus file
      x86/intel_rdt: Add diagnostics when making directories
      x86/intel_rdt: Move special case code for Haswell to a quirk function
x86/intel_rdt: Add command line options for resource director technology
      x86/intel_rdt: Turn off most RDT features on Skylake

Vikas Shivappa (29):
      x86/perf/cqm: Wipe out perf based cqm
      x86/intel_rdt/cqm: Documentation for resctrl based RDT Monitoring
      x86/intel_rdt: Introduce a common compile option for RDT
      x86/intel_rdt: Change file names to accommodate RDT monitor code
      x86/intel_rdt: Cleanup namespace to support RDT monitoring
      x86/intel_rdt: Make rdt_resources_all more readable
      x86/intel_rdt/cqm: Add RDT monitoring initialization
      x86/intel_rdt/cqm: Add RMID (Resource monitoring ID) management
      x86/intel_rdt/cqm: Add info files for RDT monitoring
      x86/intel_rdt: Prepare for RDT monitoring mkdir support
      x86/intel_rdt/cqm: Add mkdir support for RDT monitoring
      x86/intel_rdt: Change closid type from int to u32
      x86/intel_rdt/cqm: Add tasks file support
      x86/intel_rdt: Prepare to add RDT monitor cpus file support
      x86/intel_rdt/cqm: Add cpus file support
      x86/intel_rdt: Prepare for RDT monitor data support
      x86/intel_rdt/cqm: Add mon_data
      x86/intel_rdt: Separate the ctrl bits from rmdir
      x86/intel_rdt/cqm: Add rmdir support
      x86/intel_rdt/cqm: Add mount,umount support
      x86/intel_rdt: Introduce rdt_enable_key for scheduling
      x86/intel_rdt/cqm: Add sched_in support
      x86/intel_rdt/cqm: Add CPU hotplug support
      x86/intel_rdt/mbm: Add mbm counter initialization
      x86/intel_rdt/mbm: Handle counter overflow
      x86/intel_rdt/mbm: Fix MBM overflow handler during CPU hotplug
      x86/intel_rdt/cqm: Improve limbo list processing
      x86/intel_rdt/cqm: Clear the default RMID during hotcpu
      x86/intel_rdt: Modify the intel_pqr_state for better performance

Xiaochen Shen (2):
      x86/intel_rdt: Fix a silent failure when writing zero value schemata
      perf tests: Remove Intel CQM perf test

 Documentation/admin-guide/kernel-parameters.rst |    1 +
 Documentation/admin-guide/kernel-parameters.txt |    6 +
 Documentation/x86/intel_rdt_ui.txt |  323 ++++++++++++--
 MAINTAINERS |    2 +-
 arch/x86/Kconfig |   12 +-
 arch/x86/events/intel/Makefile |    2 +-
arch/x86/events/intel/cqm.c | 1766 -------------------------------------------------------------------------
 arch/x86/include/asm/intel_rdt.h |  286 ------------
 arch/x86/include/asm/intel_rdt_common.h |   27 --
 arch/x86/include/asm/intel_rdt_sched.h |   92 ++++
 arch/x86/kernel/cpu/Makefile |    2 +-
 arch/x86/kernel/cpu/intel_rdt.c |  376 +++++++++++++---
 arch/x86/kernel/cpu/intel_rdt.h |  447 +++++++++++++++++++
arch/x86/kernel/cpu/{intel_rdt_schemata.c => intel_rdt_ctrlmondata.c} | 117 ++++-
 arch/x86/kernel/cpu/intel_rdt_monitor.c |  499 +++++++++++++++++++++
arch/x86/kernel/cpu/intel_rdt_rdtgroup.c | 1248 +++++++++++++++++++++++++++++++++++++++++----------
 arch/x86/kernel/process_32.c |    2 +-
 arch/x86/kernel/process_64.c |    2 +-
 include/linux/perf_event.h |   25 +-
 include/linux/sched.h |    5 +-
 kernel/bpf/arraymap.c |   28 +-
 kernel/events/core.c |   51 +--
 kernel/trace/bpf_trace.c |   22 +-
 tools/include/linux/compiler-gcc.h |    4 +
 tools/perf/arch/arm/util/cs-etm.c |    4 +-
 tools/perf/arch/x86/include/arch-tests.h |   10 +-
 tools/perf/arch/x86/tests/Build |    1 -
 tools/perf/arch/x86/tests/arch-tests.c |    4 -
 tools/perf/arch/x86/tests/insn-x86.c |    2 +-
 tools/perf/arch/x86/tests/intel-cqm.c |  127 ------
 tools/perf/arch/x86/tests/perf-time-to-tsc.c |    2 +-
 tools/perf/arch/x86/tests/rdpmc.c |    2 +-
 tools/perf/tests/attr.c |    2 +-
 tools/perf/tests/backward-ring-buffer.c |    2 +-
 tools/perf/tests/bitmap.c |    2 +-
 tools/perf/tests/bp_signal.c |    2 +-
 tools/perf/tests/bp_signal_overflow.c |    2 +-
 tools/perf/tests/bpf.c |    4 +-
 tools/perf/tests/builtin-test.c |    4 +-
 tools/perf/tests/clang.c |    4 +-
 tools/perf/tests/code-reading.c |    2 +-
 tools/perf/tests/cpumap.c |    4 +-
 tools/perf/tests/dso-data.c |    6 +-
 tools/perf/tests/dwarf-unwind.c |    2 +-
 tools/perf/tests/event-times.c |    2 +-
 tools/perf/tests/event_update.c |    2 +-
 tools/perf/tests/evsel-roundtrip-name.c |    2 +-
 tools/perf/tests/evsel-tp-sched.c |    2 +-
 tools/perf/tests/expr.c |    2 +-
 tools/perf/tests/fdarray.c |    4 +-
 tools/perf/tests/hists_cumulate.c |    2 +-
 tools/perf/tests/hists_filter.c |    2 +-
 tools/perf/tests/hists_link.c |    2 +-
 tools/perf/tests/hists_output.c |    2 +-
 tools/perf/tests/is_printable_array.c |    2 +-
 tools/perf/tests/keep-tracking.c |    2 +-
 tools/perf/tests/kmod-path.c |    2 +-
 tools/perf/tests/llvm.c |    2 +-
 tools/perf/tests/mmap-basic.c |    2 +-
 tools/perf/tests/mmap-thread-lookup.c |    2 +-
 tools/perf/tests/openat-syscall-all-cpus.c |    2 +-
 tools/perf/tests/openat-syscall-tp-fields.c |    2 +-
 tools/perf/tests/openat-syscall.c |    2 +-
 tools/perf/tests/parse-events.c |   15 +-
 tools/perf/tests/parse-no-sample-id-all.c |    2 +-
 tools/perf/tests/perf-hooks.c |    2 +-
 tools/perf/tests/perf-record.c |    2 +-
 tools/perf/tests/pmu.c |    2 +-
 tools/perf/tests/python-use.c |    2 +-
 tools/perf/tests/sample-parsing.c |    2 +-
 tools/perf/tests/sdt.c |    4 +-
 tools/perf/tests/stat.c |    6 +-
 tools/perf/tests/sw-clock.c |    2 +-
 tools/perf/tests/switch-tracking.c |    2 +-
 tools/perf/tests/task-exit.c |    2 +-
 tools/perf/tests/tests.h |  112 ++---
 tools/perf/tests/thread-map.c |    6 +-
 tools/perf/tests/thread-mg-share.c |    2 +-
 tools/perf/tests/topology.c |    2 +-
 tools/perf/tests/unit_number__scnprintf.c |    2 +-
 tools/perf/tests/vmlinux-kallsyms.c |    2 +-
 tools/perf/util/cache.h |    3 +-
 tools/perf/util/debug.h |   11 +-
 tools/perf/util/intel-pt-decoder/intel-pt-log.h |    4 +-
 tools/perf/util/probe-event.h |    4 +-
 tools/perf/util/scripting-engines/trace-event-python.c |    3 +-
 tools/perf/util/strbuf.h |    4 +-
 tools/perf/util/trace-event-parse.c |    4 +-
 tools/perf/util/usage.c |   26 +-
 tools/perf/util/util.h |   19 +-
 90 files changed, 2987 insertions(+), 2833 deletions(-)
 delete mode 100644 arch/x86/events/intel/cqm.c
 delete mode 100644 arch/x86/include/asm/intel_rdt.h
 delete mode 100644 arch/x86/include/asm/intel_rdt_common.h
 create mode 100644 arch/x86/include/asm/intel_rdt_sched.h
 create mode 100644 arch/x86/kernel/cpu/intel_rdt.h
rename arch/x86/kernel/cpu/{intel_rdt_schemata.c => intel_rdt_ctrlmondata.c} (69%)
 create mode 100644 arch/x86/kernel/cpu/intel_rdt_monitor.c
 delete mode 100644 tools/perf/arch/x86/tests/intel-cqm.c


What I have in the tree, is what I have merged. If you have
dependencies that aren't in my tree, send them as part of a
combined series.

Bruce


Thanks,

Quanyang


On 2018年01月10日 02:19, Bruce Ashfield wrote:
This series doesn't apply to the current 4.12:

-----------------
Applying: x86/intel_rdt: Move special case code for Haswell to a quirk function
error: patch failed: arch/x86/kernel/cpu/intel_rdt.c:172
error: arch/x86/kernel/cpu/intel_rdt.c: patch does not apply
Patch failed at 0001 x86/intel_rdt: Move special case code for Haswell to a quirk function
The copy of the patch that failed is found in:
/home/bruce/poky-kernel/linux-yocto-4.12.git/.git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
---------------

Can you double check that the 4.12 you used to generate this series
matches what I have staged on git.yoctoproject.org.

Bruce

On 01/08/2018 10:20 PM, [email protected] wrote:
From: Tony Luck <[email protected]>

commit 0576113a387e0c8a5d9e24b4cd62605d1c9c0db8 upstream

No functional change, but lay the ground work for other per-model
quirks.

Signed-off-by: Tony Luck <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
Cc: Fenghua" <[email protected]>
Cc: Ravi V" <[email protected]>
Cc: "Peter Zijlstra" <[email protected]>
Cc: "Stephane Eranian" <[email protected]>
Cc: "Andi Kleen" <[email protected]>
Cc: "David Carrillo-Cisneros" <[email protected]>
Cc: Vikas Shivappa <[email protected]>
Link: http://lkml.kernel.org/r/f195a83751b5f8b1d8a78bd3c1914300c8fa3142.1503512900.git.tony.l...@intel.com
---
arch/x86/kernel/cpu/intel_rdt.c | 52 ++++++++++++++++++++++-------------------
  1 file changed, 28 insertions(+), 24 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
index dfc7c48..5af2f8f 100644
--- a/arch/x86/kernel/cpu/intel_rdt.c
+++ b/arch/x86/kernel/cpu/intel_rdt.c
@@ -172,34 +172,28 @@ static unsigned int cbm_idx(struct rdt_resource *r, unsigned int closid) * is always 20 on hsw server parts. The minimum cache bitmask length
   * allowed for HSW server is always 2 bits. Hardcode all of them.
   */
-static inline bool cache_alloc_hsw_probe(void)
+static inline void cache_alloc_hsw_probe(void)
  {
-    if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
-        boot_cpu_data.x86 == 6 &&
-        boot_cpu_data.x86_model == INTEL_FAM6_HASWELL_X) {
- struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3];
-        u32 l, h, max_cbm = BIT_MASK(20) - 1;
+    struct rdt_resource *r  = &rdt_resources_all[RDT_RESOURCE_L3];
+    u32 l, h, max_cbm = BIT_MASK(20) - 1;
  -        if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0))
-            return false;
-        rdmsr(IA32_L3_CBM_BASE, l, h);
-
-        /* If all the bits were set in MSR, return success */
-        if (l != max_cbm)
-            return false;
+    if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0))
+        return;
+    rdmsr(IA32_L3_CBM_BASE, l, h);
  -        r->num_closid = 4;
-        r->default_ctrl = max_cbm;
-        r->cache.cbm_len = 20;
-        r->cache.shareable_bits = 0xc0000;
-        r->cache.min_cbm_bits = 2;
-        r->alloc_capable = true;
-        r->alloc_enabled = true;
+    /* If all the bits were set in MSR, return success */
+    if (l != max_cbm)
+        return;
  -        return true;
-    }
+    r->num_closid = 4;
+    r->default_ctrl = max_cbm;
+    r->cache.cbm_len = 20;
+    r->cache.shareable_bits = 0xc0000;
+    r->cache.min_cbm_bits = 2;
+    r->alloc_capable = true;
+    r->alloc_enabled = true;
  -    return false;
+    rdt_alloc_capable = true;
  }
    /*
@@ -648,7 +642,7 @@ static __init bool get_rdt_alloc_resources(void)
  {
      bool ret = false;
  -    if (cache_alloc_hsw_probe())
+    if (rdt_alloc_capable)
          return true;
        if (!boot_cpu_has(X86_FEATURE_RDT_A))
@@ -690,8 +684,18 @@ static __init bool get_rdt_mon_resources(void)
return !rdt_get_mon_l3_config(&rdt_resources_all[RDT_RESOURCE_L3]);
  }
  +static __init void rdt_quirks(void)
+{
+    switch (boot_cpu_data.x86_model) {
+    case INTEL_FAM6_HASWELL_X:
+        cache_alloc_hsw_probe();
+        break;
+    }
+}
+
  static __init bool get_rdt_resources(void)
  {
+    rdt_quirks();
      rdt_alloc_capable = get_rdt_alloc_resources();
      rdt_mon_capable = get_rdt_mon_resources();







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