One thing we should keep in mind for the shadow ram thing:
Just about every chipset I have seen has shadow ram registers that can
correctly be set with the following info:
VendorID, DeviceID, Function, register, AndMask, OrMask.
This rapidly leads to a simple table something like this:
struct shadowram{
int physaddress;
u16 VendorID, DeviceID, Function;
u8 register;
u8 AndMask, OrMask};
struct shadowram s[] = {
{0xf0000, 0xabcd, 0x1234, 0x15, 0x40, 0xf8, 0x1},
{ etc.}
{0,}
};
I haven't stumbled across a chipset yet for which this would not work.
ron
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