sivakumar <[EMAIL PROTECTED]> writes: > Actually I have ported the code of the northbridge to support 845 as per > it's specification. > > Can you send me the sample intial output that I need to expect through > serial output, while booting the system with LinuxBIOS. > That might help me in debugging further.
It depends some on how verbose your debug messages are: >From the p4dpr-igm: > >LinuxBIOS-1.0.0.9rc1Normal Fri Oct 25 21:54:54 MDT 2002 starting... >Power failed >Restarting pci clocks > > >LinuxBIOS-1.0.0.9rc1Normal Fri Oct 25 21:54:54 MDT 2002 starting... >Ram1 >Ram2 >Reading SPD data... >setting based on SPD data... >done >Ram3 >Ram Enable 1 >Ram Enable 2 >Ram Enable 3 >Ram Enable 4 >Ram Enable 5 >Ram Enable 6 >Ram Enable 7 >Ram Enable 8 >Ram Enable 9 >Ram Enable 10 >Ram Enable 11 >Ram4 >Bank 01 Side 00 Spot checking: 00000000-0007ffff >Bank 02 Side 00 Spot checking: 08000000-0807ffff >Bank 03 Side 00 Spot checking: 10000000-1007ffff >Bank 03 Side 01 Spot checking: 14000000-1407ffff >Ram5 >Initializing ECC state... >ECC state initialized. >Ram6 >Copying LinuxBIOS to ram. >Jumping to LinuxBIOS. >LinuxBIOS-1.0.0.9rc1Normal Fri Oct 25 21:54:54 MDT 2002 booting... >Finding PCI configuration type. >handle_superio port 0x0, defaultport 0x2e >handle_superio Using port 0x2e >Scanning PCI bus...done >Allocating PCI resources...done. >Enabling PCI resourcess...done. >Initializing PCI devices... >PCI devices initialized >totalram: 4096M >Initializing CPU #0 >microcode_info: sig = 0x00000f24 pf=0x00000002 rev = 0x00000000 >microcode updated from revision 0 to 16 >Enabling cache...done. >Setting up local apic...done. >CPU #0 Initialized >clocks_per_usec: 2397 >Initializing CPU #6 >microcode_info: sig = 0x00000f24 pf=0x00000002 rev = 0x00000000 >microcode updated from revision 0 to 16 >Initializing CPU #1 >Enabling cache...microcode_info: sig = 0x00000f24 pf=0x00000002 rev = >0x00000010Initializing CPU #7 >done. >microcode updated from revision 16 to 16 >set power on after power fail >microcode_info: sig = 0x00000f24 pf=0x00000002 rev = 0x00000010 >handle_superio port 0x2e, defaultport 0x2e >Enabling cache...microcode updated from revision 16 to 16 >Setting up local apic...handle_superio Using port 0x2e >done. >done. >Setting up local apic...Enabling cache...CPU #6 Initialized >done. >done. >Setting up local apic...CPU #1 Initialized >done. >CPU #7 Initialized >handle_superio port 0x2e, defaultport 0x2e >handle_superio Using port 0x2e >Copying IRQ routing tables to 0xf0000...done. > >Welcome to elfboot, the open sourced starter. >January 2002, Eric Biederman. >Version 1.2 > >Loading Etherboot version: 5.1.2rc7.eb10 >ROM segment 0x0000 length 0xfbf8 reloc 0x00020000 >Etherboot 5.1.2rc7.eb10 (GPL) ELF64 ELF (Multiboot) for [EEPRO100][E1000][IDE] >CPU 2470 Mhz >Boot from (N)etwork (D)isk (F)loppy or from (L)ocal? >Probing pci nic... >[E1000]The PCI BIOS has not enabled this device! >Updating PCI command 0003->0007. pci_bus 03 pci_device_fn 20 >Ethernet addr: 00:30:48:12:3D:1D >e1000: Valid Link not detected >[EEPRO100]The PCI BIOS has not enabled this device! >Updating PCI command 0003->0007. pci_bus 04 pci_device_fn 10 >Ethernet addr: 00:30:48:12:37:0F > >Searching for server (DHCP)... >..Me: 192.168.0.27, Server: 192.168.0.252, Gateway 192.168.0.252 >Loading 192.168.0.252:dual-amd-boot2.ebi ...(ELF)... Loading Linux version: >................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ > You shouldn't have the double start of LinuxBIOS, that exists to work around bugs in the board. >Copying LinuxBIOS to ram. >Jumping to LinuxBIOS. >LinuxBIOS-1.0.0.9rc1Normal Fri Oct 25 21:54:54 MDT 2002 booting... The above is definitely generic code and should be present. And I would expect the check points in the generic ram setup to be useful. Eric _______________________________________________ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
