Peter Stuge <[EMAIL PROTECTED]> writes: > On Tue, Mar 04, 2003 at 11:25:18AM -0500, Jeremy Jackson wrote: > > Another idea on the subject: > > > > On some chipsets, the entire range of supported processors have MMX and > > maybe SSE/SSE2. MMX gives 8 extra 64 bit registers (nobody uses > > floating-point in LinuxBIOS, right?) that can be used as 32bit. They > > can't be used as address/index/base, but only for data. See the MOVD > > instruction. > > Likewise, st0..st7 in the FPU could be used as a stack-like 8x64bit data > storage, IIRC.
There are no register to register moves from the integer registers to the floating point registers, unless I missed some. The data we care about is integer data, and so any extra registers just act as overflow locations that are used instead of the stack. > I seem to remember that Pentium MMX CPUs share st* space > with MMX registers however, so for those platforms one of them will have > to do. As I recall you can only access one of them at a time, but it doesn't matter if there are no register->register transfers. Anyway for those wondering where I am at. I currently have a compiler that gets as far as intermediate code for a useful subset of C expressions. Now I just have to do some optimizer work, and an actual code generator. Mostly for the optimizer side I am initially concerned about doing a good job of register allocation. Hopefully I can have something someone else can play with by the start of next week... Eric _______________________________________________ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
