ron minnich <[EMAIL PROTECTED]> writes:
> OK, I have applied Yh Lu's patches for the most part. In almost all cases
> they are tyan 2880-specific. There are three things I can see that might
> affect others:
>
> #ifdef some-variable
> no longer works in many places, it has to be
> #if some-variable == 1
>
> to work.
>
>
> - for the new config too, there is no longer a default for _RAMBASE,
> due to PPC and K8 differences
Hmm. We can't have a per architecture default _RAMBASE?
As long as there is an error if you don't set it I guess that
is ok.
> raminit.c sees the following changes:
> Index: src/northbridge/amd/amdk8/raminit.c
Ron on these kind of things please use diff -u or cvs diff -u
it is much, much, much more readable.
> ===================================================================
> RCS file: /cvsroot/freebios/freebios2/src/northbridge/amd/amdk8/raminit.c,v
> retrieving revision 1.12
> diff -r1.12 raminit.c
> 921a922,927
> > //BY LYH add IOMMU 64M APERTURE
> > PCI_ADDR(0, 0x18, 3, 0x94), 0xffff8000, 0x00000f70,
> > PCI_ADDR(0, 0x18, 3, 0x90), 0xffffff80, 0x00000002,
> > PCI_ADDR(0, 0x18, 3, 0x98), 0x0000000f, 0x00068300,
> >
> > //BY LYH END
> 1119c1125,1141
> <
> ---
With YhLu's observation that Function 2 dram base addresses are per
memory controller local addresses there are a number of pieces in here
that just need to be fixed.
Hopefully I can get at it tomorrow. The current code base does not
have the second memory controller working for me.
> > static void fill_last(unsigned long node_id,unsigned long base)
> > {
> > //BY LYH //Fill next base reg with right value
> > unsigned i;
> > unsigned base_reg;
> > base &=0xffff0000;
> > device_t device;
> > for(device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1); device
>
> > += PCI_DEV(0, 1, 0)) {
> > for(i=node_id+1;i<=7;i++) {
> > base_reg=0x40+(i<<3);
> > pci_write_config32(device,base_reg,base);
> > }
> > }
> > //BY LYH END
> > }
> >
> 1128a1151
> >
> 1145a1169
> >
> 1254,1256c1278,1280
> < print_debug("csbase=");
> < print_debug_hex32(csbase);
> < print_debug("\r\n");
> ---
> > // print_debug("csbase=");
> > // print_debug_hex32(csbase);
> > // print_debug("\r\n");
> 1285a1310,1312
> > //BY LYH
> > fill_last(ctrl->node_id, tom_k<<2);
> > //BY LYH END
> 1288,1291c1315,1319
> < if(ctrl->node_id==1) {
> < pci_write_config32(ctrl->f2, DRAM_CSBASE, 0x00000001);
> <
> < }
> ---
> > dump_pci_device(PCI_DEV(0, 0x18, 1));
> >
> > // if(ctrl->node_id==1) {
> > // pci_write_config32(ctrl->f2, DRAM_CSBASE, 0x00000001);
> > // }
>
>
> and the amd8111 sees this:
>
> Index: src/southbridge/amd/amd8111/amd8111_ldtstop.c
> ===================================================================
> RCS file:
> /cvsroot/freebios/freebios2/src/southbridge/amd/amd8111/amd8111_ldtstop.c,v
>
> retrieving revision 1.4
> diff -r1.4 amd8111_ldtstop.c
> 22c22
> < pci_write_config16(dev, 0x48, pci_read_config16(dev,0x48) & ~CPUPIN);
> ---
> > pci_write_config32(dev, 0x48, pci_read_config32(dev,0x48) & ~CPUPIN);
>
That looks to be a noop so it should not cause trouble.
> If this is trouble, let me know.
>
> You are going to have to set _RAMBASE in your mainboard Config.lb
> now.
Unfortunate but it should be a large problem.
Ron while we are thinking about it where should we place tables on the
ARM? It has a ROM chip as the first thing in memory.
Eric
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