On Fri, Oct 03, 2003 at 09:32:30AM -0600, Eric W. Biederman wrote:
> Patches welcome if someone wants to change the options.
Attached patch changes romcc to internally have a set of features,
instead of CPU name. CPU name sets the feature set for the CPU,
and users can also set individual feature bits.
--
Takeshi
Index: romcc.c
===================================================================
RCS file: /cvsroot/freebios/freebios2/util/romcc/romcc.c,v
retrieving revision 1.24
diff -u -r1.24 romcc.c
--- romcc.c 17 Sep 2003 12:18:40 -0000 1.24
+++ romcc.c 6 Oct 2003 08:55:10 -0000
@@ -15258,15 +15258,11 @@
*/
#define X86_4_8BIT_GPRS 1
-/* Recognized x86 cpu variants */
-#define BAD_CPU 0
-#define CPU_I386 1
-#define CPU_P3 2
-#define CPU_P4 3
-#define CPU_K7 4
-#define CPU_K8 5
+/* x86 features */
+#define X86_MMX_REGS (1<<0)
+#define X86_XMM_REGS (1<<1)
-#define CPU_DEFAULT CPU_I386
+#define BAD_CPU -1
/* The x86 register classes */
#define REGC_FLAGS 0
@@ -15423,26 +15419,36 @@
[REGC_IMM8] = { REGC_IMM8_FIRST, REGC_IMM8_LAST },
};
-static int arch_encode_cpu(const char *cpu)
+static int arch_encode_cpu(const char *feature)
{
struct cpu {
const char *name;
int cpu;
} cpus[] = {
- { "i386", CPU_I386 },
- { "p3", CPU_P3 },
- { "p4", CPU_P4 },
- { "k7", CPU_K7 },
- { "k8", CPU_K8 },
- { 0, BAD_CPU }
+ { "i386", 0 },
+ { "p2", X86_MMX_REGS },
+ { "p3", X86_MMX_REGS | X86_XMM_REGS },
+ { "p4", X86_MMX_REGS | X86_XMM_REGS },
+ { "k7", X86_MMX_REGS },
+ { "k8", X86_MMX_REGS | X86_XMM_REGS },
+ { "c3", X86_MMX_REGS },
+ { "c3-2", X86_MMX_REGS | X86_XMM_REGS }, /* Nehemiah */
+ { 0, BAD_CPU }
};
struct cpu *ptr;
- for(ptr = cpus; ptr->name; ptr++) {
- if (strcmp(ptr->name, cpu) == 0) {
- break;
+
+ if (strcmp(feature, "mmx") == 0)
+ return X86_MMX_REGS;
+ else if (strcmp(feature, "sse") == 0)
+ return X86_XMM_REGS;
+ else if (strncmp(feature, "cpu=", 4) == 0) {
+ for(ptr = cpus; ptr->name; ptr++) {
+ if (strcmp(ptr->name, feature+4) == 0)
+ break;
}
+ return ptr->cpu;
}
- return ptr->cpu;
+ return BAD_CPU;
}
static unsigned arch_regc_size(struct compile_state *state, int class)
@@ -15651,16 +15657,10 @@
REGCM_GPR32 | REGCM_GPR32_8 |
REGCM_DIVIDEND32 | REGCM_DIVIDEND64 |
REGCM_IMM32 | REGCM_IMM16 | REGCM_IMM8 | REGCM_FLAGS;
- switch(state->cpu) {
- case CPU_P3:
- case CPU_K7:
+ if (state->cpu & X86_MMX_REGS)
avail_mask |= REGCM_MMX;
- break;
- case CPU_P4:
- case CPU_K8:
- avail_mask |= REGCM_MMX | REGCM_XMM;
- break;
- }
+ if (state->cpu & X86_XMM_REGS)
+ avail_mask |= REGCM_XMM;
return avail_mask;
}
@@ -18056,7 +18056,7 @@
int last_argc;
int debug;
int optimize;
- cpu = CPU_DEFAULT;
+ cpu = 0;
label_prefix = "";
ofilename = "auto.inc";
optimize = 0;
@@ -18090,12 +18090,14 @@
argv += 2;
argc -= 2;
}
- else if (strncmp(argv[1], "-mcpu=", 6) == 0) {
- cpu = arch_encode_cpu(argv[1] + 6);
- if (cpu == BAD_CPU) {
- arg_error("Invalid cpu specified: %s\n",
- argv[1] + 6);
+ else if (strncmp(argv[1], "-m", 2) == 0) {
+ int x;
+ x = arch_encode_cpu(argv[1] + 2);
+ if (x == BAD_CPU) {
+ arg_error("Invalid CPU feature specified: %s\n",
+ argv[1] + 2);
}
+ cpu |= x;
argv++;
argc--;
}
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