On Fri, 14 Nov 2003, Svante Signell wrote:
I have now run the lmbench3-0-a3 tests. For the correctly working 1.4
GHz Tualatin CPU the latency numbers shows jumps from 2ns to 6ns at 16k
array size and from 6ns to 120ns at 265k array size. I assume this
indicates correctly working level 1 and 2 caches.
yes.
For the erroneous motherboard with a 1.3GHz Tualatin CPU the numbers are around 400ns independent of array size. The only thing changig is that the latency numbers increase to 440-460ns for large values of the stride. My interpretation is that not even the L1 cache is working properly. All other tests indicate a _very_ slow CPU, around 7MHz is measured by lmbench (BTW how good is this value?) compared to the expected 1.3GHz. Two questions immediately arise.
weird. I have no idea what's going on here. Something is really wrong.
I don't think I can comment with much precision here, but...
My early experience with disabled cache is that the system gets REALLY slow. PIII's (I think) will read a full cache line for every word it needs. That means that if you have a 32 byte cache line and read the entire line one 32 bit word at a time (8 accesses) the PIII will read that entire cache line 8 times, one for each word access. This may apply only to code fetches.
It gets really rediculous when this is happening while executing code over the ISA bus (from ROM).
Cheers! Ty
-- Tyson D Sawyer iRobot Corporation Senior Systems Engineer Military Systems Division [EMAIL PROTECTED] Robots for the Real World 603-654-3400 ext 206 http://www.irobot.com
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