Devi Priya wrote:
From the AMD data sheet:
Thanks for ur suggestion.
My flash is 4 MB. My processor can address up to 4 GB physical address space. That means after power-on, in shematic should I map the flash memory like 0xFFC00000-0xFFFFFFFF and
0x00000000-0x003FFFFF? 0r in upper address, is it enough to map the 256KB region to the Flash ie 0xFFFC0000-0xFFFFFFFF? and the lower address to 0x00000000-0x003FFFFF
From: ron minnich <[EMAIL PROTECTED]> To: Devi Priya <[EMAIL PROTECTED]> CC: [EMAIL PROTECTED] Subject: Re: sc1200? Date: Wed, 17 Dec 2003 22:07:00 -0700 (MST)
at power-on, on all chipsets for PCs I have used, FLASH is mapped at BOTH 0xffffff0 and 0xffff0.
The Core Logic module positively decodes memory addresses 000F0000h-000FFFFFh (64 KB) and FFFC0000h-FFFFFFFFh (256 KB) at reset. These memory cycles cause the Core Logic module to claim the cycle, and generate an ISA bus memory cycle with ROMCS# asserted. The Core Logic module can also be configured to respond to memory addresses FF000000h-FFFFFFFFh (16 MB) and 000E0000h-000FFFFFh (128 KB). 8- or 16-bit wide ROM is supported. BOOT16 strap determines the width after reset. MCR[14,3] (Offset 34h) in the General Configuration Block allows program control of the width. Flash ROM is supported in the Core Logic module by enabling the ROMCS# signal on write accesses to the ROM region. Normally only read cycles are passed to the ISA bus, and the ROMCS# signal is suppressed for write cycles. When the ROM Write Enable bit (F0 Index 52h[1]) is set, a write access to the ROM address region causes a write cycle to occur with MEMW#,WR# and ROMCS# asserted.
The Boot Flash supported by the SC1200/SC1201 can be up to 16 MB. It is supported with the ROMCS# signal.
DOCCS# — Asserted on memory read/write transactions from/to a programmable window.
• ROMCS# — Asserted on memory read/write to upper 16 MB of address space. Configurable via the ROM Mask register (F0 Index 6Eh).
• DOCR# — DOCR# is asserted on memory read transactions from DOCCS# window (i.e., when both DOCCS# and MEMR# are active, DOCR# is active; otherwise, it is inactive).
• DOCW — DOCW# is asserted on memory write transactions to DOCCS# window (i.e., when both DOCCS# and MEMW# are active, DOCW# is active; otherwise, it is inactive).
• RD#, WR# — The signals IOR#, IOW#, MEMR#, and MEMW# are combined into two signals: RD# is asserted on I/O read or memory read; WR# is asserted on I/O write or memory write.
Memory devices that use ROMCS# or DOCCS# as their chip select signal can be configured to support an 8-bit or 16-bit data bus via bits 3 and 6 of the MCR register. Such devices can also be configured as zero wait states devices (regardless of the data bus width) via bits 9 and 10 of the MCR register.
The DiskOnChip chip select signal (DOCCS#) is asserted on any memory read or memory write transaction from/to a programmable address range. The address range is pro-grammable via the DOCCS#Base Address and Control registers (F0 Index 78h and 7Ch). The base address must be on an address boundary, the size of the range. Signal DOCCS# can also be used to interface to NAND Flash devices together with signals DOCW# and DOCR#.
See application note AMD Geode™ SC1200/SC2200/ SC3200 Processors: External NAND Flash Memory Circuit for details.
This you'll have to get from AMD. It goes into using the DOC for boot ROM and also as a general storage device. It also contains IPL and SPL code along with the boot procedure, memory map, etc.
-Bari
_______________________________________________ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
