diff -uNr ./freebios2/src/mainboard/tyan/s2850/hypertransport.c ../freebios2.03262004.release/src/mainboard/tyan/s2850/hypertransport.c --- ./freebios2/src/mainboard/tyan/s2850/hypertransport.c 2004-01-12 12:00:42.000000000 -0800 +++ ../freebios2.03262004.release/src/mainboard/tyan/s2850/hypertransport.c 1969-12-31 16:00:00.000000000 -0800 @@ -1,54 +0,0 @@ -/* coherent hypertransport initialization for AMD64 - * - * tyan mainboard specific setup code from lyh - * - * This code is licensed under GPL. - */ - - static void coherent_ht_mainboard(unsigned cpus) -{ - - static const unsigned int register_values[] = { - PCI_ADDR(0, 0x18, 0, 0x84), 0x88ff9c05, 0x00000020, - PCI_ADDR(0, 0x18, 0, 0xa4), 0x88ff9c05, 0x770000d0, - PCI_ADDR(0, 0x18, 0, 0xc4), 0x88ff9c05, 0x770000d0, - - - PCI_ADDR(0, 0x18, 0, 0x88), 0xfffff0ff, 0x00000000, - PCI_ADDR(0, 0x18, 0, 0xa8), 0xfffff0ff, 0x00000000, - PCI_ADDR(0, 0x18, 0, 0xc8), 0xfffff0ff, 0x00000000, - - PCI_ADDR(0, 0x18, 0, 0x94), 0xff0000ff, 0x00ff0000, - PCI_ADDR(0, 0x18, 0, 0xb4), 0xff0000ff, 0x00000000, - PCI_ADDR(0, 0x18, 0, 0xd4), 0xff0000ff, 0x00000000, - - }; - int i; - int max; - - - device_t dev; - unsigned where; - unsigned long reg; - - print_debug("setting up ht links....\r\n"); - max = sizeof(register_values)/sizeof(register_values[0]); - for(i = 0; i < max; i += 3) { -#if 0 - print_debug_hex32(i); - print_debug(": "); - print_debug_hex32(register_values[i]); - print_debug(" <-"); - print_debug_hex32(register_values[i+2]); - print_debug("\r\n"); -#endif - dev = register_values[i] & ~0xff; - where = register_values[i] & 0xff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - pci_write_config32(dev, where, reg); - } - print_debug("done\r\n"); - -} diff -uNr ./freebios2/src/mainboard/tyan/s2880/hypertransport.c ../freebios2.03262004.release/src/mainboard/tyan/s2880/hypertransport.c --- ./freebios2/src/mainboard/tyan/s2880/hypertransport.c 2003-09-25 15:04:19.000000000 -0700 +++ ../freebios2.03262004.release/src/mainboard/tyan/s2880/hypertransport.c 1969-12-31 16:00:00.000000000 -0800 @@ -1,63 +0,0 @@ -/* coherent hypertransport initialization for AMD64 - * - * tyan mainboard specific setup code from lyh - * - * This code is licensed under GPL. - */ - - static void coherent_ht_mainboard(unsigned cpus) -{ - - static const unsigned int register_values[] = { - PCI_ADDR(0, 0x18, 0, 0x84), 0x88ff9c05, 0x11000020, - PCI_ADDR(0, 0x18, 0, 0xa4), 0x88ff9c05, 0x11000020, - PCI_ADDR(0, 0x18, 0, 0xc4), 0x88ff9c05, 0x770000d0, - PCI_ADDR(0, 0x19, 0, 0x84), 0x88ff9c05, 0x770000d0, - PCI_ADDR(0, 0x19, 0, 0xa4), 0x88ff9c05, 0x11000020, - PCI_ADDR(0, 0x19, 0, 0xc4), 0x88ff9c05, 0x770000d0, - - - PCI_ADDR(0, 0x18, 0, 0x88), 0xfffff0ff, 0x00000400, - PCI_ADDR(0, 0x18, 0, 0xa8), 0xfffff0ff, 0x00000500, - PCI_ADDR(0, 0x18, 0, 0xc8), 0xfffff0ff, 0x00000000, - PCI_ADDR(0, 0x19, 0, 0x88), 0xfffff0ff, 0x00000000, - PCI_ADDR(0, 0x19, 0, 0xa8), 0xfffff0ff, 0x00000500, - PCI_ADDR(0, 0x19, 0, 0xc8), 0xfffff0ff, 0x00000000, - - PCI_ADDR(0, 0x18, 0, 0x94), 0xff0000ff, 0x00ff0000, - PCI_ADDR(0, 0x18, 0, 0xb4), 0xff0000ff, 0x00000000, - PCI_ADDR(0, 0x18, 0, 0xd4), 0xff0000ff, 0x00000000, - PCI_ADDR(0, 0x19, 0, 0x94), 0xff0000ff, 0x00000000, - PCI_ADDR(0, 0x19, 0, 0xb4), 0xff0000ff, 0x00000000, - PCI_ADDR(0, 0x19, 0, 0xd4), 0xff0000ff, 0x00000000, - - }; - int i; - int max; - - - device_t dev; - unsigned where; - unsigned long reg; - - print_debug("setting up ht links....\r\n"); - max = sizeof(register_values)/sizeof(register_values[0]); - for(i = 0; i < max; i += 3) { -#if 0 - print_debug_hex32(i); - print_debug(": "); - print_debug_hex32(register_values[i]); - print_debug(" <-"); - print_debug_hex32(register_values[i+2]); - print_debug("\r\n"); -#endif - dev = register_values[i] & ~0xff; - where = register_values[i] & 0xff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - pci_write_config32(dev, where, reg); - } - print_debug("done\r\n"); - -} diff -uNr ./freebios2/src/mainboard/tyan/s2882/auto.c ../freebios2.03262004.release/src/mainboard/tyan/s2882/auto.c --- ./freebios2/src/mainboard/tyan/s2882/auto.c 2004-03-25 10:04:17.000000000 -0800 +++ ../freebios2.03262004.release/src/mainboard/tyan/s2882/auto.c 2004-03-25 19:44:26.000000000 -0800 @@ -114,9 +114,6 @@ return smbus_read_byte(device, address); } -/* include mainboard specific ht code */ -#include "hypertransport.c" - #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "sdram/generic_sdram.c" diff -uNr ./freebios2/src/mainboard/tyan/s2882/Config.lb ../freebios2.03262004.release/src/mainboard/tyan/s2882/Config.lb --- ./freebios2/src/mainboard/tyan/s2882/Config.lb 2004-03-25 01:31:09.000000000 -0800 +++ ../freebios2.03262004.release/src/mainboard/tyan/s2882/Config.lb 2004-03-25 19:21:44.000000000 -0800 @@ -124,9 +124,6 @@ ### ### Romcc output ### -#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E" -#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc" -#mainboardinit .failover.inc makerule ./failover.E depends "$(MAINBOARD)/failover.c" @@ -143,8 +140,7 @@ end makerule ./auto.inc depends "./romcc ./auto.E" - action "./romcc -O -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E" -# action "./romcc -mcpu=k8 -O ./auto.E > auto.inc" + action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E" end mainboardinit cpu/k8/enable_mmx_sse.inc mainboardinit ./auto.inc diff -uNr ./freebios2/src/mainboard/tyan/s2882/hypertransport.c ../freebios2.03262004.release/src/mainboard/tyan/s2882/hypertransport.c --- ./freebios2/src/mainboard/tyan/s2882/hypertransport.c 2003-08-28 08:08:43.000000000 -0700 +++ ../freebios2.03262004.release/src/mainboard/tyan/s2882/hypertransport.c 1969-12-31 16:00:00.000000000 -0800 @@ -1,61 +0,0 @@ -/* coherent hypertransport initialization for AMD64 - * - * tyan mainboard specific setup code from lyh - * - * This code is licensed under GPL. - */ - - static void coherent_ht_mainboard(unsigned cpus) -{ - static const unsigned int register_values[] = { - PCI_ADDR(0, 0x18, 0, 0x84), 0x88ff9c05, 0x11000020, - PCI_ADDR(0, 0x18, 0, 0xa4), 0x88ff9c05, 0x11000020, - PCI_ADDR(0, 0x18, 0, 0xc4), 0x88ff9c05, 0x770000d0, - PCI_ADDR(0, 0x19, 0, 0x84), 0x88ff9c05, 0x770000d0, - PCI_ADDR(0, 0x19, 0, 0xa4), 0x88ff9c05, 0x11000020, - PCI_ADDR(0, 0x19, 0, 0xc4), 0x88ff9c05, 0x770000d0, - - - PCI_ADDR(0, 0x18, 0, 0x88), 0xfffff0ff, 0x00000400, - PCI_ADDR(0, 0x18, 0, 0xa8), 0xfffff0ff, 0x00000500, - PCI_ADDR(0, 0x18, 0, 0xc8), 0xfffff0ff, 0x00000000, - PCI_ADDR(0, 0x19, 0, 0x88), 0xfffff0ff, 0x00000000, - PCI_ADDR(0, 0x19, 0, 0xa8), 0xfffff0ff, 0x00000500, - PCI_ADDR(0, 0x19, 0, 0xc8), 0xfffff0ff, 0x00000000, - - PCI_ADDR(0, 0x18, 0, 0x94), 0xff0000ff, 0x00ff0000, - PCI_ADDR(0, 0x18, 0, 0xb4), 0xff0000ff, 0x00000000, - PCI_ADDR(0, 0x18, 0, 0xd4), 0xff0000ff, 0x00000000, - PCI_ADDR(0, 0x19, 0, 0x94), 0xff0000ff, 0x00000000, - PCI_ADDR(0, 0x19, 0, 0xb4), 0xff0000ff, 0x00000000, - PCI_ADDR(0, 0x19, 0, 0xd4), 0xff0000ff, 0x00000000, - - }; - int i; - int max; - - - device_t dev; - unsigned where; - unsigned long reg; - - print_debug("setting up ht links....\r\n"); - max = sizeof(register_values)/sizeof(register_values[0]); - for(i = 0; i < max; i += 3) { -#if 0 - print_debug_hex32(i); - print_debug(": "); - print_debug_hex32(register_values[i]); - print_debug(" <-"); - print_debug_hex32(register_values[i+2]); - print_debug("\r\n"); -#endif - dev = register_values[i] & ~0xff; - where = register_values[i] & 0xff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - pci_write_config32(dev, where, reg); - } - print_debug("done\r\n"); -} diff -uNr ./freebios2/src/mainboard/tyan/s2885/auto.c ../freebios2.03262004.release/src/mainboard/tyan/s2885/auto.c --- ./freebios2/src/mainboard/tyan/s2885/auto.c 2004-03-25 10:17:36.000000000 -0800 +++ ../freebios2.03262004.release/src/mainboard/tyan/s2885/auto.c 2004-03-25 19:44:54.000000000 -0800 @@ -1,4 +1,5 @@ -#define ASSEMBLY 1 +#define ASSEMBLY 1 + #include #include #include @@ -39,23 +40,24 @@ pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); } +#define REV_B_RESET 0 static void memreset_setup(void) { - if (is_cpu_pre_c0()) { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 - } else { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 - } +#if REV_B_RESET==1 + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 +#else + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 +#endif + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); } static void memreset(int controllers, const struct mem_controller *ctrl) { - if (is_cpu_pre_c0()) { - udelay(800); - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 - udelay(90); - } + udelay(800); +#if REV_B_RESET==1 + outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 +#endif + udelay(90); } static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) @@ -82,20 +84,21 @@ * [3] Route to Link 2 */ - uint32_t ret = 0x00010101; /* default row entry */ + uint32_t ret=0x00010101; /* default row entry */ static const unsigned int rows_2p[2][2] = { { 0x00050101, 0x00010404 }, { 0x00010404, 0x00050101 } }; - if (maxnodes > 2) { + if(maxnodes>2) { print_debug("this mainboard is only designed for 2 cpus\r\n"); - maxnodes = 2; + maxnodes=2; } - if (!(node >= maxnodes || row >= maxnodes)) { - ret = rows_2p[node][row]; + + if (!(node>=maxnodes || row>=maxnodes)) { + ret=rows_2p[node][row]; } return ret; @@ -151,63 +154,53 @@ { .udev = PCI_DEV(0, 0x18, 0), .upos = 0xc0, - .devreg = 0xe2, - .mindev = 1, - }, + .devreg = 0xe0, + }, { .udev = PCI_DEV(0, 0x18, 0), .upos = 0x80, - .devreg = 0xe6, - .mindev = 5, - - }, + .devreg = 0xe4, + }, }; int needs_reset; - enable_lapic(); init_timer(); - if (cpu_init_detected()) { asm("jmp __cpu_reset"); } - distinguish_cpu_resets(); if (!boot_cpu()) { stop_this_cpu(); } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); - setup_s2885_resource_map(); needs_reset = setup_coherent_ht_domain(); // needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0); needs_reset |= ht_setup_chains(ht_c, sizeof(ht_c)/sizeof(ht_c[0])); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset - \r\t"); soft_reset(); } #if 0 dump_pci_devices(); #endif - #if 0 print_pci_devices(); #endif - enable_smbus(); - #if 0 dump_spd_registers(&cpu[0]); #endif - memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); #if 0 dump_pci_devices(); +#endif +#if 0 dump_pci_device(PCI_DEV(0, 0x18, 1)); #endif @@ -219,7 +212,11 @@ print_debug_hex32(msr.hi); print_debug_hex32(msr.lo); print_debug("\r\n"); +#endif +/* +#if 0 ram_check(0x00000000, msr.lo+(msr.hi<<32)); +#else #if TOTAL_CPUS < 2 // Check 16MB of memory @ 0 ram_check(0x00000000, 0x00100000); @@ -228,4 +225,5 @@ ram_check(0x80000000, 0x80100000); #endif #endif +*/ } diff -uNr ./freebios2/src/mainboard/tyan/s2885/Config.lb ../freebios2.03262004.release/src/mainboard/tyan/s2885/Config.lb --- ./freebios2/src/mainboard/tyan/s2885/Config.lb 2004-03-25 01:31:09.000000000 -0800 +++ ../freebios2.03262004.release/src/mainboard/tyan/s2885/Config.lb 2004-03-25 19:21:05.000000000 -0800 @@ -120,10 +120,6 @@ ### ### Romcc output ### -#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E" -#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc" -#mainboardinit .failover.inc - makerule ./failover.E depends "$(MAINBOARD)/failover.c" action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E" @@ -141,8 +137,7 @@ makerule ./auto.inc depends "./romcc ./auto.E" - action "./romcc -O -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E" -# action "./romcc -mcpu=k8 -O ./auto.E > auto.inc" + action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E" end mainboardinit cpu/k8/enable_mmx_sse.inc diff -uNr ./freebios2/src/mainboard/tyan/s2885/mainboard.c ../freebios2.03262004.release/src/mainboard/tyan/s2885/mainboard.c --- ./freebios2/src/mainboard/tyan/s2885/mainboard.c 2004-03-25 01:31:09.000000000 -0800 +++ ../freebios2.03262004.release/src/mainboard/tyan/s2885/mainboard.c 2004-03-24 19:57:40.000000000 -0800 @@ -87,10 +87,11 @@ pci_write_config8(dev, 0x43, byte); } #endif +#if 0 static void onboard_scsi_fixup(void) { struct device *dev; -#if 0 +#if 1 unsigned char i,j,k; for(i=0;i<=6;i++) { @@ -119,6 +120,7 @@ // print_mem(); // amd8111_enable_rom(); } +#endif #if 0 static void vga_fixup(void) { // we do this right here because: @@ -153,8 +155,8 @@ // case CONF_PASS_PRE_PCI: // case CONF_PASS_POST_PCI: case CONF_PASS_PRE_BOOT: - if (conf->fixup_scsi) - onboard_scsi_fixup(); +// if (conf->fixup_scsi) + // onboard_scsi_fixup(); // if (conf->fixup_vga) // vga_fixup(); printk_debug("mainboard fixup pass %d done\r\n", diff -uNr ./freebios2/src/mainboard/tyan/s2885/resourcemap.c ../freebios2.03262004.release/src/mainboard/tyan/s2885/resourcemap.c --- ./freebios2/src/mainboard/tyan/s2885/resourcemap.c 2004-03-25 10:04:18.000000000 -0800 +++ ../freebios2.03262004.release/src/mainboard/tyan/s2885/resourcemap.c 2004-03-25 19:20:31.000000000 -0800 @@ -252,8 +252,8 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ - PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x04010207, - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x06050007, + PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06010207, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000007, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff -uNr ./freebios2/src/northbridge/amd/amdk8/incoherent_ht.c ../freebios2.03262004.release/src/northbridge/amd/amdk8/incoherent_ht.c --- ./freebios2/src/northbridge/amd/amdk8/incoherent_ht.c 2004-03-25 09:50:06.000000000 -0800 +++ ../freebios2.03262004.release/src/northbridge/amd/amdk8/incoherent_ht.c 2004-03-25 13:31:24.000000000 -0800 @@ -182,7 +182,6 @@ return needs_reset; } - static int ht_setup_chain(device_t udev, unsigned upos) { /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. @@ -246,62 +245,29 @@ device_t udev; unsigned upos; unsigned devreg; - unsigned mindev; -}; - -static int ht_setup_chains(const struct ht_chain *ht_c, int ht_c_num) +}; +static int ht_setup_chainx(device_t udev, unsigned upos, unsigned next_unitid) { - /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a cpu has multiple - * non Coherent links the appropriate bus registers for the - * links needs to be programed to point at bus 0. - */ - unsigned next_unitid, last_unitid; - int reset_needed; + unsigned last_unitid; unsigned uoffs; - unsigned upos; - device_t udev; - int i; - - /* Make certain the HT bus is not enumerated */ - ht_collapse_previous_enumeration(0); - - reset_needed = 0; - next_unitid = 1; - - - for(i=0;i 1 - pci_write_config8(PCI_DEV(0,0x19,1), ht_c[i].devreg, 0); -#endif -#if CONFIG_MAX_CPUS > 2 - pci_write_config8(PCI_DEV(0,0x1a,1), ht_c[i].devreg, 0); - pci_write_config8(PCI_DEV(0,0x1b,1), ht_c[i].devreg, 0); -#endif + int reset_needed=0; + uoffs = PCI_HT_HOST_OFFS; - upos = ht_c[i].upos; - udev = ht_c[i].udev; do { uint32_t id; uint8_t pos; unsigned flags, count; device_t dev = PCI_DEV(0, 0, 0); last_unitid = next_unitid; - + id = pci_read_config32(dev, PCI_VENDOR_ID); /* If the chain is enumerated quit */ if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0x0000)) { break; - } + } pos = ht_lookup_slave_capability(dev); if (!pos) { print_err("HT link capability not found\r\n"); @@ -326,26 +292,74 @@ next_unitid += count; } while((last_unitid != next_unitid) && (next_unitid <= 0x1f)); -#if 0 - pci_write_config8(PCI_DEV(0,0x18,1), ht_c[i].devreg, tmp); + if(reset_needed!=0) next_unitid |= 0xffff0000; + return next_unitid; +} +static int ht_setup_chains(const struct ht_chain *ht_c, int ht_c_num) +{ + /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. + * On most boards this just happens. If a cpu has multiple + * non Coherent links the appropriate bus registers for the + * links needs to be programed to point at bus 0. + */ + unsigned next_unitid; + int reset_needed; + unsigned upos; + device_t udev; + int i; + + /* Make certain the HT bus is not enumerated */ + ht_collapse_previous_enumeration(0); + + reset_needed = 0; + next_unitid = 1; + + + for(i=0;i 1 - pci_write_config8(PCI_DEV(0,0x19,1), ht_c[i].devreg, tmp); + pci_write_config32(PCI_DEV(0,0x19,1), ht_c[i].devreg, reg); #endif #if CONFIG_MAX_CPUS > 2 - pci_write_config8(PCI_DEV(0,0x1a,1), ht_c[i].devreg, tmp); - pci_write_config8(PCI_DEV(0,0x1b,1), ht_c[i].devreg, tmp); + pci_write_config32(PCI_DEV(0,0x1a,1), ht_c[i].devreg, reg); + pci_write_config32(PCI_DEV(0,0x1b,1), ht_c[i].devreg, reg); #endif -#else - pci_write_config8(PCI_DEV(0,0x18,1), ht_c[i].devreg, ht_c[i].mindev); + //Store dev min + reg8 = next_unitid & 0xff ; + upos = ht_c[i].upos; + udev = ht_c[i].udev; + + next_unitid = ht_setup_chainx(udev,upos,next_unitid); + + if((next_unitid & 0xffff0000) == 0xffff0000) { + reset_needed |= 1; + next_unitid &=0x0000ffff; + } + + //set dev min + pci_write_config8(PCI_DEV(0,0x18,1), ht_c[i].devreg+2, reg8); #if CONFIG_MAX_CPUS > 1 - pci_write_config8(PCI_DEV(0,0x19,1), ht_c[i].devreg, ht_c[i].mindev); + pci_write_config8(PCI_DEV(0,0x19,1), ht_c[i].devreg+2, reg8); #endif #if CONFIG_MAX_CPUS > 2 - pci_write_config8(PCI_DEV(0,0x1a,1), ht_c[i].devreg, ht_c[i].mindev); - pci_write_config8(PCI_DEV(0,0x1b,1), ht_c[i].devreg, ht_c[i].mindev); + pci_write_config8(PCI_DEV(0,0x1a,1), ht_c[i].devreg+2, reg8); + pci_write_config8(PCI_DEV(0,0x1b,1), ht_c[i].devreg+2, reg8); +#endif + //Set dev max + reg8 = (next_unitid-1) & 0xff ; + pci_write_config8(PCI_DEV(0,0x18,1), ht_c[i].devreg+3, reg8); +#if CONFIG_MAX_CPUS > 1 + pci_write_config8(PCI_DEV(0,0x19,1), ht_c[i].devreg+3, reg8); #endif +#if CONFIG_MAX_CPUS > 2 + pci_write_config8(PCI_DEV(0,0x1a,1), ht_c[i].devreg+3, reg8); + pci_write_config8(PCI_DEV(0,0x1b,1), ht_c[i].devreg+3, reg8); #endif - } return reset_needed;