I'm posting what I had at the time I got it working, maybe it can go into CVS for safe keeping.
freebios/src/mainboard/soyo/6ba+ directory contents attached. -- Jeremy Jackson Coplanar Networks (519)897-1516 http://www.coplanar.net
arch i386 mainboardinit cpu/i386/entry16.inc mainboardinit cpu/i386/entry32.inc ldscript cpu/i386/entry16.lds ldscript cpu/i386/entry32.lds mainboardinit cpu/i386/reset16.inc ldscript cpu/i386/reset16.lds
#option SERIAL_SUPERIO_BASEADDRESS=0x3f0 option HAVE_PIRQ_TABLE=1 #mainboardinit superio/SMC/fdc37c67x/setup_serial.inc mainboardinit superio/ITE/it8671f/setup_serial.inc mainboardinit pc80/serial.inc mainboardinit arch/i386/lib/console.inc northbridge intel/440bx southbridge intel/piix4e #mainboardinit cpu/p6/earlymtrr.inc mainboardinit ram/dump_northbridge.inc mainboardinit ram/ramtest.inc mainboardinit mainboard/soyo/6ba+/do_ramtest.inc superio ITE/it8671f #option ENABLE_FIXED_AND_VARIABLE_MTRRS option PIIX4_DEVFN=0x38 option NO_KEYBOARD=1 option ZKERNEL_START=0xfffc0000 option ZKERNEL_MASK=0x7f option L440BX=1 #option SMC_BASE=0x3F0 option CONFIG_UDELAY_TSC=1 option CONFIG_LINUXBIOS_ENABLE_IDE=1 option CONFIG_LINUXBIOS_LEGACY_IDE=1 option CONFIG_COMPRESS=0 object mainboard.o object irq_tables.o cpu p6 cpu p5 option RAM_TEST=1
# These are keyword-value pairs. # a : separates the keyword from the value # the value is arbitrary text delimited by newline. # continuation, if needed, will be via the \ at the end of a line # comments are indicated by a '#' as the first character. # the keywords are case-INSENSITIVE owner: Jeremy Jackson email: [EMAIL PROTECTED] status: stable explanation: everything works, but I fried my only board the next day flash-types: 128K 256K DIP32 payload-types: etherboot # e.g. linux, plan 9, wince, etc. OS-types: Linux # e.g. "Plan 9 interrupts don't work on this chipset" OS-issues: None console-types:Serial # vga is unsupported, unstable, or stable vga:unsupported # Last-known-good follows the internationl date standard: day/month/year last-known-good: 30/09/2004 Comments: You must set CONFIG_COMPRESS to 0 in your config file (see the example) Links: Mainboard-revision: # What other mainboards are like this one? List them here. AKA:
# Sample config file for Intel 430TX chipset on the Smartcore P5 # This will make a target directory of ./smartcore-p5 target /data/build/linuxbios/target # ASUS CUA main board mainboard soyo/6ba+ # option HAVE_PIRQ_TABLE=1 # Enable Serial Console for debugging option SERIAL_CONSOLE=1 option NO_KEYBOARD=1 #nooption NO_KEYBOARD #keyboard pc80 option INBUF_COPY=1 option DEFAULT_CONSOLE_LOGLEVEL=9 #option MAXIMUM_CONSOLE_LOGLEVEL=10 option DEBUG=1 option USE_GENERIC_ROM=1 option ROM_SIZE=131072 option PAYLOAD_SIZE=65536 # MEMORY TESTING USING MEMTEST option USE_ELF_BOOT=1 payload /var/local/setup/etherboot.org/eb-5.2.5-eepro100.elf #nooption RAMTEST
mov $0x00000000, %eax
mov $0x0009ffff, %ebx
mov $16, %ecx
CALLSP(ramtest)
/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM */ #define IRQ_SLOT_COUNT 7 #include <arch/pirq_routing.h> const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ 32+16*7, /* there can be total 7 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x07<<3)|0x0, /* Where the interrupt router lies (dev) */ 0x1c00, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x7000, /* Device */ 0, /* Crap (miniport) */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x73, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x10<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, {0x00,(0x11<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, {0x00,(0x12<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, {0x00,(0x13<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x5, 0x0}, {0x00,(0x07<<3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, {0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, {0x70,(0x00<<3)|0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, } };
#include <printk.h>
#include <pci.h>
#include <cpu/p5/io.h>
// this needs to be moved about a bit to northbridge.c etc.
void mainboard_fixup()
{
struct pci_dev *pm_pcidev;
// struct pci_dev *host_bridge_pcidev;
struct pci_dev *nic_pcidev;
unsigned smbus_io, pm_io;
unsigned int i, j;
printk_debug("intel_mainboard_fixup()\n");
#if 1
pm_pcidev = pci_find_device(0x8086, 0x7113, 0);
nic_pcidev = pci_find_device(0x8086, 0x1229, 0);
// host_bridge_pcidev = pci_find_slot(0, PCI_DEVFN(0,0));
#endif
#if 1
pci_write_config_byte(nic_pcidev, 0x3c, 5);
#endif
#if 0
{
u8 byte;
u16 word;
u32 dword;
for(i = 0; i < 8; i++) {
pci_read_config_byte(host_bridge_pcidev, 0x60 +i, &byte);
printk_debug("DRB[i] = 0x%02x\n", byte);
}
pci_read_config_byte(host_bridge_pcidev, 0x57, &byte);
printk_debug("DRAMC = 0x%02x\n", byte);
pci_read_config_byte(host_bridge_pcidev, 0x74, &byte);
printk_debug("RPS = 0x%02x\n", byte);
pci_read_config_word(host_bridge_pcidev, 0x78, &word);
printk_debug("PGPOL = 0x%04x\n", word);
pci_read_config_dword(host_bridge_pcidev, 0x50, &dword);
printk_debug("NBXCFG = 0x%04x\n", dword);
}
#endif
#if 0
printk_debug("Reset Control Register\n");
outb(((inb(0xcf9) & 0x04) | 0x02), 0xcf9);
printk_debug("port 92\n");
outb((inb(0x92) & 0xFE), 0x92);
printk_debug("Disable Nmi\n");
outb(0, 0x70);
printk_debug("enabling smbus\n");
#if 0
smbus_io = NewPciIo(0x10);
#else
smbus_io = 0xFFF0;
#endif
pci_write_config_dword(pm_pcidev, 0x90, smbus_io | 1); /* iobase addr */
pci_write_config_byte(pm_pcidev, 0xd2, (0x4 << 1) | 1); /* smbus enable */
pci_write_config_word(pm_pcidev, 0x4, 1); /* iospace enable */
printk_debug("enable pm functions\n");
#if 0
pm_io = NewPciIo(0x40);
#else
pm_io = 0xFF80;
#endif
pci_write_config_dword(pm_pcidev, 0x40, pm_io | 1); /* iobase addr */
pci_write_config_byte(pm_pcidev, 0x80, 1); /* enable pm io address */
printk_debug("disabling smi\n");
/* GLBEN */
outw(0x00, pm_io + 0x20);
/* GLBCTL */
outl((1 << 24), pm_io + 0x28);
printk_debug("Disable more pm stuff\n");
/* PMEN */
outw((1 << 8), pm_io + 0x02);
/* PMCNTRL */
outw((0x5 << 10) , pm_io + 0x4);
/* PMTMR */
outl(0, pm_io + 0x08);
/* GPEN */
outw(0, pm_io + 0x0e);
/* PCNTRL */
outl(0, pm_io + 0x10);
/* GLBSTS */
/* DEVSTS */
/* GLBEN see above */
/* GLBCTL see above */
/* DEVCTL */
outl(0, pm_io + 0x2c);
/* GPIREG */
/* GPOREG */
printk_debug("Set the subsystem vendor id\n");
pci_write_config_word(host_bridge_pcidev, 0x2c, 0x8086);
printk_debug("Disabling pm stuff in pci config space\n");
#define MAX_COUNTERS
#ifndef MAX_COUNTERS
/* counters to 0 */
#define WHICH_COUNTERS(min,max) min
#else
/* max out the counters */
#define WHICH_COUNTERS(min,max) max
#endif
/* CNTA */
pci_write_config_dword(pm_pcidev, 0x44, WHICH_COUNTERS(0x004000f0, 0xFFFFFFFF));
/* CNTB */
pci_write_config_dword(pm_pcidev, 0x48, WHICH_COUNTERS(0x00000400, 0x007c07df));
/* GPICTL */
pci_write_config_dword(pm_pcidev, 0x4c, 0);
/* DEVRESD */
pci_write_config_dword(pm_pcidev, 0x50, 0);
/* DEVACTA */
pci_write_config_dword(pm_pcidev, 0x54, 0);
/* DEVACTB */
pci_write_config_dword(pm_pcidev, 0x58, 0);
/* DEVRESA */
pci_write_config_dword(pm_pcidev, 0x5c, 0);
/* DEVRESB */
pci_write_config_dword(pm_pcidev, 0x60, 0);
/* DEVRESC */
pci_write_config_dword(pm_pcidev, 0x64, 0); /* might kill the serial port */
/* DEVRESE */
pci_write_config_dword(pm_pcidev, 0x68, 0);
/* DEVRESF */
pci_write_config_dword(pm_pcidev, 0x6c, 0);
/* DEVRESG */
pci_write_config_dword(pm_pcidev, 0x70, 0);
/* DEVRESH */
pci_write_config_dword(pm_pcidev, 0x74, 0);
/* DEVRESI */
pci_write_config_dword(pm_pcidev, 0x78, 0);
/* DEVRESJ */
pci_write_config_dword(pm_pcidev, 0x7c, 0);
#endif
#if 1
/* Verify that smi is disabled */
printk_debug("Testing SMI\r\n");
{
u32 value;
pci_read_config_dword(pm_pcidev, 0x58, &value);
pci_write_config_dword(pm_pcidev, 0x58, value | (1 << 25));
}
outb(inb(0xb2), 0xb2);
printk_debug("SMI disabled\r\n");
#endif
#if 0
for(i = 0; i < 255; i++) {
printk_debug("%08x\r\n", i);
__rdtsc_delay2(1000000000UL, pm_io);
}
#endif
southbridge_fixup();
}
