--- raminit.c.ori	2004-11-24 17:51:58.000000000 -0800
+++ raminit.c.4r	2004-12-14 14:28:34.000000000 -0800
@@ -587,6 +587,7 @@
 struct dimm_size {
 	unsigned long side1;
 	unsigned long side2;
+	unsigned rank;
 };
 
 static struct dimm_size spd_get_dimm_size(unsigned device)
@@ -596,6 +597,7 @@
 	int value, low;
 	sz.side1 = 0;
 	sz.side2 = 0;
+	sz.rank = 0;
 
 	/* Note it might be easier to use byte 31 here, it has the DIMM size as
 	 * a multiple of 4MB.  The way we do it now we can size both
@@ -637,11 +639,11 @@
 	if (value < 0) goto hw_err;
 	if (value == 1) goto out;
 //		print_debug("side2 banks: 0x");         print_debug_hex32(value);         print_debug(" \r\n");
-#if 1
-	if ((value != 2) && (value != 4 )) {
+
+	if ( (value != 2) && (value != 4) ) {
 		goto val_err;
 	}
-#endif
+	sz.rank = value;
 
 	/* Start with the symmetrical case */
 	sz.side2 = sz.side1;
@@ -665,6 +667,7 @@
 hw_err:
 	sz.side1 = 0;
 	sz.side2 = 0;
+	sz.rank = 0;
  out:
 	return sz;
 }
@@ -679,6 +682,9 @@
 	}
 	map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
 	map &= ~(0xf << (index * 4));
+	if(sz.rank == 4) {
+		map &= ~(0xf << ( (index + 2) * 4));
+	}
 
 	/* For each base register.
 	 * Place the dimm size in 32 MB quantities in the bits 31 - 21.
@@ -691,6 +697,9 @@
 	/* Make certain side1 of the dimm is at least 32MB */
 	if (sz.side1 >= (25 +3)) {
 		map |= (sz.side1 - (25 + 3)) << (index *4);
+		if(sz.rank == 4) {
+			map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4);
+		}
 		base0 = (1 << ((sz.side1 - (25 + 3)) + 21)) | 1;
 	}
 	/* Make certain side2 of the dimm is at least 32MB */
@@ -711,12 +720,19 @@
 	/* Set the appropriate DIMM base address register */
 	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
 	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
+	if(sz.rank == 4) {
+	        pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0);
+	        pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1);
+	}
 	pci_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map);
 	
 	/* Enable the memory clocks for this DIMM */
 	if (base0) {
 		dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
 		dch |= DCH_MEMCLK_EN0 << index;
+		if(sz.rank == 4) {
+			dch |= DCH_MEMCLK_EN0 << (index + 2);
+		}
 		pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
 	}
 }