Ronald G Minnich wrote:
> On 2 Jan 2001, Eric W. Biederman wrote:
>
> >
> > Ron I thought of a passable work around to the no ram problem, during
> > memory init. Turn on L1 cache and initialize it. Then you run in cache
> > while you are initializing memory. It's not fool proof and I still need
> > to see if I can do it, but it looks to me like this will allow memory
> > init to be done in C code.
>
> the trick will be making the l1 init withouut having the chipset touch
> memory .Any writes to memory can cause either SDRAM death or a cihpset
> lockup (as in l440gx)
>
> ron
If you can fit all your C code into L1 cache this could work. L2 cache doesn't need to
be turned on
and the only reason I've ever seen the need to initialize DRAM is because the assembly
code in the
BIOS generates an error code and halts the system if it's not done or if there isn't
any DRAM in the
system. I have this question into Intel, AMD and VIA as a general question for their
chipsets. The
answer may vary based on each northbridge design. Ollie, any thoughts on this for SIS
northbridges?
As a tangent to LinuxBIOS. Think about a very small stripped down Linux kernel
something the size of
say QNX and a small application that could boot from a DOC and only run in L1 and/or
L2 without any
DRAM. It would scream running at current core speeds.
Bari
