* Eric W Biederman <[EMAIL PROTECTED]> [020817 21:37]:
> Stefan Reinauer <[EMAIL PROTECTED]> writes:
>
> > * Eric W Biederman <[EMAIL PROTECTED]> [020815 05:14]:
> > > Stefan Reinauer <[EMAIL PROTECTED]> writes:
> > >
> > > > * Eric W Biederman <[EMAIL PROTECTED]> [020808 13:50]:
> > > > > For the record 5.1 is the bleeding edge developer version of etherboot
> > > > > and it almost worked :) The 5.0.x is the stable series, and since
> > > > > 5.0.6 or so has native LinuxBIOS support.
> > > >
> > > > I saw the IDE code that went into 5.1 and wanted to give it a try while
> > > > still being able to network boot the machine for testing. Unfortunately
> > > > typing "L" at the prompt just hangs the machine, but etherboot probably
> > > > does not even know where it should load the kernel from, so i have to
> > > > look deeper into this
> > >
> > > Now that you have something that works, how has the playing gone?
> >
> > I did not get to look into it until after your latest CVS updates. I'm
> > currently not able to build either of .elf, .ebi, .lzebi, ...
> > Is there any secrets necessary to build these due to the new device
> > probing scheme?
>
> I have a left over dependency in the Makefile to config-pci.o instead of
> config.o Sorry.
>
> For targets I have simplified it slightly and there is just .elf and .lzelf.
Ah, good. I only found two places where virt_to_bus is definitely
needed. With below patch applied, I get the following output when
chainloading etherboot (I have some rc1 cvs in flash and latest cvs as
elfimage) It loads itself the second time, but hangs after this.
Does this fail because it tries to relocate to the same position?
--------------------------------------------------------------------
Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.2
37:init_bytes() - zkernel_start:0xfffe0000 zkernel_mask:0x0000ffff
Found ELF candiate at offset 0
New segment addr 0x94000 size 0x89e4 offset 0x60 filesize 0x40c4
(cleaned up) New segment addr 0x94000 size 0x89e4 offset 0x60 filesize
0x40c4
Loading Segment: addr: 0x0000000000094000 memsz: 0x00000000000089e4
filesz: 0x00
000000000040c4
Clearing Segment: addr: 0x00000000000980c4 memsz: 0x0000000000004920
Jumping to boot code
ROM segment 0xc1ae length 0x2c12 reloc 0x9400
Etherboot 5.1.2rc1 (GPL) Tagged ELF for [RTL8139]
Boot from (N)etwork or from (L)ocal? CPU 234 Mhz
N
Probing...[RTL8139]Found Realtek 8139 ROM address 0x0000
- The PCI BIOS has not enabled this device!
Updating PCI command 0003->0007. pci_bus 00 pci_device_fn 78
ioaddr 0X1000, addr 00:E0:4C:88:02:A5 100Mbps full-duplex
Searching for server (DHCP)...
Me: 192.168.0.13, Server: 192.168.0.23, Gateway 192.168.0.50
Loading 192.168.0.23:vmlinux.elf (ELF)... Loading Etherboot version:
5.1.2rc2
done
ROM segment 0xc1ae length 0x2c12 reloc 0x00021000
Etherboot 5.1.2rc2 (GPL) Tagged ELF for [RTL8139]
Relocating _text from: [000260cc,0002ed1c) to [01bf73b0,01c00000)
Boot from (N)etwork or from (L)ocal? CPU 234 Mhz
N
Probing...[RTL8139]Found Realtek 8139 ROM address 0x0000
- ioaddr 0X1000, addr 00:E0:4C:88:02:A5 100Mbps full-duplex
Searching for server (DHCP)...
Me: 192.168.0.13, Server: 192.168.0.23, Gateway 192.168.0.50
Loading 192.168.0.23:vmlinux.elf (ELF)... Loading Etherboot version:
5.1.2rc2
done
--------------------------------------------------------------------
Stefan
--
The x86 isn't all that complex - it just doesn't make a lot of
sense. -- Mike Johnson, Leader of 80x86 Design at AMD
Microprocessor Report (1994)
Index: Makefile
===================================================================
RCS file: /cvsroot/etherboot/etherboot/etherboot-5.1/src/Makefile,v
retrieving revision 1.12
diff -u -r1.12 Makefile
--- Makefile 17 Aug 2002 00:52:13 -0000 1.12
+++ Makefile 17 Aug 2002 23:36:45 -0000
@@ -373,8 +373,8 @@
$(LD32) -Ttext 0x10000 $(LDBINARY32) -o $@ $<
# general ruls for generating .img files
-bin32/%.tmp: bin32/%.o bin32/config-pci.o bin32/pci.o $(STDDEPS32)
- $(LD32) $(LDFLAGS32) -o $@ $(START32) bin32/config-pci.o $< bin32/pci.o
$(LIBS32)
+bin32/%.tmp: bin32/%.o bin32/config.o bin32/pci.o $(STDDEPS32)
+ $(LD32) $(LDFLAGS32) -o $@ $(START32) bin32/config.o $< bin32/pci.o $(LIBS32)
@$(SIZE32) $@ | $(CHECKSIZE)
bin32/%.img: bin32/%.tmp $(MAKEDEPS)
Index: rtl8139.c
===================================================================
RCS file: /cvsroot/etherboot/etherboot/etherboot-5.1/src/rtl8139.c,v
retrieving revision 1.7
diff -u -r1.7 rtl8139.c
--- rtl8139.c 17 Aug 2002 00:52:13 -0000 1.7
+++ rtl8139.c 17 Aug 2002 23:36:47 -0000
@@ -319,7 +319,7 @@
#ifdef DEBUG_RX
printf("rx ring address is %X\n",(unsigned long)rx_ring);
#endif
- outl((unsigned long)rx_ring, ioaddr + RxBuf);
+ outl((unsigned long)virt_to_bus(rx_ring), ioaddr + RxBuf);
/* Start the chip's Tx and Rx process. */
outl(0, ioaddr + RxMissed);
@@ -358,7 +358,7 @@
tx_buffer[len++] = '\0';
}
- outl((unsigned long)tx_buffer, ioaddr + TxAddr0 + cur_tx*4);
+ outl((unsigned long)virt_to_bus(tx_buffer), ioaddr + TxAddr0 + cur_tx*4);
outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len,
ioaddr + TxStatus0 + cur_tx*4);
