Can anyone confirm that this is a problem? Or am I barking up the wrong tree?
Eric Poulsen wrote: >Okay, I got it to work again. This is weird, but I figured out what the >issue is. I think the build system for LB (at least for the Epia-M >branch) is bad. I don't have any experience with romcc or building >BIOSes, but I do have quite a bit of experience with C,C++, and using >makefiles -- something seems very wrong here, especially when you look >at the details of the two build processes shown below. IMHO, "make >clean" should set you back to the beginning (as it seems to), and a >compile after that should fix any weirdnesses with linking. > >Just in case it's not clear, in both examples below, there are NO "real" >code changes between them, only configuration changes. Also, this is >with my own Epia-ML branch (derived from Epia-M) -- the only difference >is that I removed the ieee1394 init code in auto.c and edited the >Config.lb for the mainboard so that it doesn't init the floppy and the >CF card reader, which don't exist on the ML. I was having the exact >same issues with the out-of-the-box Epia-M branch. When I built it (both >Epia-M and Epia-ML branches) successfully in the past, I _never_ used >make clean because I figured buildtarget would fix any issues, >especially since a 'make' after 'buildtarget' resulted in recompilation >of several files. > >In short, my recent use of 'make clean' seems to be hosing the process. > >This _DOES NOT WORK_ (but it should): > >(pseudocode -- not literal) >]Set CONFIG_CONSOLE_VGA=1, CONFIG_PCI_ROM_RUN=1 in Config.lb >]buildtarget via/epia-m >]cd via/epia-m/epia-m >]make clean >]make >][Bunches of link errors because of overlapping sections] >|set ROM_IMAGE_SIZE to 0x12000 (previously 0x10000), as per Stefan's >suggestion. >buildtarget >make clean >make >[successful compile] >cat vga_bios linuxbios.rom > lb.rom >flashrom >[Reboot] >Crash, exception 13 just after vga write protect > >This _DOES WORK_ > >Start with default epia-m config.lb >buildtarget >[compiles clean, but no vga options on -- If I were to flash and reboot, >this would work as-is, sans VGA] >Edit Config.lb add CONFIG_CONSOLE_VGA=1 >buildtarget >make [_IMPORTANT_ -- NOTICE THERE IS NO 'make clean' LINE!] >[compiles clean] >Edit Config.lb add CONFIG_PCI_ROM_RUN=1 >buildtarget >make [_IMPORTANT_ -- NOTICE THERE IS NO 'make clean' LINE!] >[compiles clean] >cat vga_bios linuxbios.rom >flashrom >[reboot] >[Everything works -- boots, VGA works, etc. ] >[Important thing to note about the above is that the ROM_IMAGE_SIZE _was >not_ increased] > > > > >Eric Poulsen wrote: > > > >>I've been trying to accomplish several things: >> >>1) LB on Via Epia ML 5000 2) VGA working 3) Figuring out weird boot >>errors that seem to be "fixed" by the factory BIOS. Running >>memtest86+ under LB. >> >>I _was_ on step 3, but in the course of events, I went back to step >>2. VGA is now NOT working again, but with a different error; see >>below. >> >>Since I was messing around with making an ML tree, adding a bit of >>custom stuff, and removing initializations for devices that don't >>exist on the ML (floppy, CF reader), I figured I had done something >>wrong. >> >>Soooo, I went back to the "stock" LinuxBIOSv2, revision 2100, known >>to work with the Epia M. This particular revision worked for me, >>albeit with the long delay at the beginning because of the firewire >>search. >> >>Essentially, whenever, I add ... >> >>#VGA Console option CONFIG_CONSOLE_VGA=1 option CONFIG_PCI_ROM_RUN=1 >> >>... to the Config.lb, it doesn't work, giving the error below. >> >>Mysteriously, my "weird boot crashes that are fixed by factory CMOS" >> problems aren't exhibiting themselves. >> >>Unfortunately, I cannot run memtest86 under LB without VGA. >> >>Any ideas? >> >>-------------------------------------------------------------------- >> >>0 >> >>LinuxBIOS-1.1.8.0Fallback Sat Apr 29 22:12:48 PDT 2006 starting... >>Enabling mainboard devices Enabling shadow ram vt8623 init starting >>Detecting Memory Number of Banks 04 Number of Rows 0d Priamry DRAM >>width08 No Columns 0a MA type e0 Bank 0 (*16 Mb) 10 No Physical Banks >>01 Total Memory (*16 Mb) 10 CAS Supported 2 2.5 3 Cycle time at CL X >>(nS)50 Cycle time at CL X-0.5 (nS)60 Cycle time at CL X-1 (nS)75 >>Starting at CAS 3 We can do CAS 2.5 We can do CAS 2 tRP 48 tRCD 48 >>tRAS 28 Low Bond 00 High Bondbe Setting DQS delay7evt8623 done >>00:06 11 23 31 06 00 30 22 00 00 00 06 00 00 00 00 10:08 00 00 d0 00 >>00 00 00 00 00 00 00 00 00 00 00 20:00 00 00 00 00 00 00 00 00 00 00 >>00 00 00 00 00 30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 >>40:00 18 88 80 82 44 00 00 18 99 88 80 82 44 00 00 50:c8 de cf 88 e0 >>07 00 00 e0 00 10 10 10 10 00 00 60:02 ff 00 30 d6 32 01 2a 42 2d 43 >>58 00 44 00 00 70:82 48 00 01 01 08 50 00 01 00 00 00 00 00 00 02 >>80:0f 65 00 00 80 00 00 00 02 00 00 00 00 00 00 00 90:00 00 00 00 00 >>00 00 00 00 00 00 00 00 00 00 00 a0:02 c0 20 00 07 02 00 1f 04 00 00 >>00 2f 02 04 00 b0:00 00 00 00 80 00 00 00 88 00 00 00 00 00 00 00 >>c0:01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0:00 00 00 00 00 >>00 00 00 00 00 00 00 00 00 00 00 e0:00 dd 00 00 00 00 01 00 40 00 00 >>00 00 00 00 00 f0:00 00 00 00 00 00 12 13 00 00 00 00 00 00 00 00 AGP >> Doing MTRR init. Copying LinuxBIOS to ram. Jumping to LinuxBIOS. >>LinuxBIOS-1.1.8.0Fallback Sat Apr 29 22:12:48 PDT 2006 booting... >>clocks_per_usec: 838 Enumerating buses... Finding PCI configuration >>type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled >>APIC_CLUSTER: 0 enabled PCI: pci_scan_bus for bus 0 PCI: 00:00.0 >>[1106/3123] enabled PCI: 00:01.0 [1106/b091] enabled Disabling static >>device: PCI: 00:0a.0 Disabling static device: PCI: 00:0a.1 In >>vt8235_enable 1106 3038. PCI: 00:10.0 [1106/3038] enabled In >>vt8235_enable 1106 3038. PCI: 00:10.1 [1106/3038] enabled In >>vt8235_enable 1106 3038. PCI: 00:10.2 [1106/3038] enabled In >>vt8235_enable 1106 3104. PCI: 00:10.3 [1106/3104] enabled In >>vt8235_enable 1106 3177. Initialising Devices PCI: 00:11.0 >>[1106/3177] enabled In vt8235_enable 1106 0571. PCI: 00:11.1 >>[1106/0571] enabled In vt8235_enable 1106 3059. PCI: 00:11.5 >>[1106/3059] enabled In vt8235_enable ffff ffff. In vt8235_enable 1106 >>3065. PCI: 00:12.0 [1106/3065] enabled PCI: pci_scan_bus for bus 1 >>PCI: 01:00.0 [1106/3122] enabled PCI: pci_scan_bus returning with >>max=01 vt1211 enabling PNP devices. PNP: 002e.0 enabled vt1211 >>enabling PNP devices. PNP: 002e.1 enabled vt1211 enabling PNP >>devices. PNP: 002e.2 enabled vt1211 enabling PNP devices. PNP: 002e.3 >>enabled vt1211 enabling PNP devices. PNP: 002e.b enabled PCI: >>pci_scan_bus returning with max=01 done Allocating resources... >>Reading resources... Done reading resources. Allocating VGA resource >>PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 >>Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting >>PCI_BRIDGE_CTL_VGA for bridge Root Device Setting resources... I >>would set ram size to 0x40000 Kbytes PCI: 00:10.0 20 <- [0x0000001800 >>- 0x000000181f] io PCI: 00:10.1 20 <- [0x0000001820 - 0x000000183f] >>io PCI: 00:10.2 20 <- [0x0000001840 - 0x000000185f] io PCI: 00:10.3 >>10 <- [0x00febff000 - 0x00febff0ff] mem PNP: 002e.0 60 <- >>[0x00000003f0 - 0x00000003f7] io PNP: 002e.0 70 <- [0x0000000006 - >>0x0000000006] irq PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] drq >> PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] io PNP: 002e.1 70 <- >>[0x0000000007 - 0x0000000007] irq PNP: 002e.1 74 <- [0x0000000003 - >>0x0000000003] drq PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] io >>PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] irq PNP: 002e.3 60 <- >>[0x00000002f8 - 0x00000002ff] io PNP: 002e.3 70 <- [0x0000000003 - >>0x0000000003] irq PNP: 002e.b 60 <- [0x000000ec00 - 0x000000ecff] io >>PCI: 00:11.1 20 <- [0x0000001860 - 0x000000186f] io PCI: 00:11.5 10 >><- [0x0000001000 - 0x00000010ff] io PCI: 00:12.0 10 <- [0x0000001400 >>- 0x00000014ff] io PCI: 00:12.0 14 <- [0x00fec00000 - 0x00fec000ff] >>mem Done setting resources. Done allocating resources. Enabling >>resourcess... PCI: 00:00.0 cmd <- 146 PCI: 00:01.0 bridge ctrl <- >>000f PCI: 00:01.0 cmd <- 147 PCI: 01:00.0 cmd <- 143 PCI: 00:10.0 >>subsystem <- 00/00 PCI: 00:10.0 cmd <- 141 PCI: 00:10.1 subsystem <- >>00/00 PCI: 00:10.1 cmd <- 141 PCI: 00:10.2 subsystem <- 00/00 PCI: >>00:10.2 cmd <- 141 PCI: 00:10.3 subsystem <- 00/00 PCI: 00:10.3 cmd >><- 142 PCI: 00:11.0 cmd <- 147 PNP: 002e.0 - enabling PNP: 002e.1 - >>enabling PNP: 002e.2 - enabling PNP: 002e.3 - enabling PNP: 002e.b - >>enabling PCI: 00:11.1 cmd <- 147 PCI: 00:11.5 subsystem <- 00/00 PCI: >>00:11.5 cmd <- 141 PCI: 00:12.0 cmd <- 1c3 done. Initializing >>devices... Root Device init PCI: 00:10.0 init PCI: 00:10.1 init PCI: >>00:10.2 init PCI: 00:10.3 init PCI: 00:11.0 init vt8235 init RTC Init >> Invalid CMOS LB checksum pci_routing_fixup: dev is 0001ad40 setting >>firewire setting usb Assigning IRQ 5 to 0:10.0 Readback = 5 >>pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 >>Assigning IRQ 9 to 0:10.1 Readback = 9 pci_level_irq: lower order >>bits are wrong: want 0x0, got 0x20 Assigning IRQ 9 to 0:10.2 Readback >>= 9 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 >>Assigning IRQ 5 to 0:10.3 Readback = 5 pci_level_irq: lower order >>bits are wrong: want 0x0, got 0x20 setting vt8235 Assigning IRQ 5 to >>0:11.1 Readback = 5 pci_level_irq: lower order bits are wrong: want >>0x0, got 0x20 Assigning IRQ 9 to 0:11.5 Readback = 9 pci_level_irq: >>lower order bits are wrong: want 0x0, got 0x20 setting ethernet >>Assigning IRQ 5 to 0:12.0 Readback = 5 pci_level_irq: lower order >>bits are wrong: want 0x0, got 0x20 setting vga Assigning IRQ 5 to >>1:0.0 Readback = 5 pci_level_irq: lower order bits are wrong: want >>0x0, got 0x20 setting pci slot setting cardbus slot setting riser >>slot PNP: 002e.0 init PNP: 002e.1 init PNP: 002e.2 init PNP: 002e.3 >>init PNP: 002e.b init PCI: 00:11.1 init Enabling VIA IDE. ide_init: >>enabling compatibility IDE addresses enables in reg 0x42 0x0 enables >>in reg 0x42 read back as 0x0 enables in reg 0x40 0x13 enables in reg >>0x40 read back as 0x13 enables in reg 0x9 0x8a enables in reg 0x9 >>read back as 0x8a command in reg 0x4 0x7 command in reg 0x4 reads >>back as 0x7 PCI: 00:11.5 init PCI: 00:12.0 init Configuring VIA Rhine >>LAN APIC_CLUSTER: 0 init Initializing CPU #0 CPU: vendor Centaur >>device 673 Enabling cache >> >>Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB >> Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs Setting >>variable MTRR 0, base: 0MB, range: 128MB, type WB Setting >>variable MTRR 1, base: 128MB, range: 64MB, type WB Setting >>variable MTRR 2, base: 192MB, range: 32MB, type WB DONE variable >>MTRRs Clear out the extra MTRR's >> >>MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled >> >>Disabling local apic...done. CPU #0 Initialized PCI: 00:00.0 init >>VT8623 random fixup ... Frame buffer at d0000000 PCI: 00:01.0 init >>VT8623 AGP random fixup ... PCI: 01:00.0 init VGA random fixup ... >>INSTALL REAL-MODE IDT DO THE VGA BIOS found VGA: vid=1106, did=3122 >>rom base, size: fffc0000 write_protect_vgabios bus/devfn = 0x100 >>Unexpected Exception: 13 @ 10:000121c3 - Halting Code: 0 eflags: >>00010012 eax: 00000012 ebx: 00024530 ecx: 00023fa8 edx: 00000012 edi: >>00018a90 esi: ffff946b ebp: 00023f84 esp: 00023f84 >> >> >> >> >> >> > > > > > -- linuxbios mailing list [email protected] http://www.openbios.org/mailman/listinfo/linuxbios
