Hi!
I have a small Geode LX + CS5536 board (433MHz, 128MB DDR, UART2 as serial).
With the help of those changes in GX2/OLPC target (patch attached) I
have managed to boot it at least (it still doesn't load VSA nor boot any
payload). The changes should be mostly marked with comment '// GX3' to
ease further development.
This is really ugly hack...sorry guys. But some day I hope there will be
correct LX support with separate target. I can't provide any timetable
though nor say how much I can work on it.
But hey... linuxbios rules and I am keen to help.
thanks,
Indrek
diff -r -b -B -u LinuxBIOSv2/src/cpu/amd/model_gx2/cpubug.c LinuxBIOSv2_ad4/src/cpu/amd/model_gx2/cpubug.c
--- LinuxBIOSv2/src/cpu/amd/model_gx2/cpubug.c 2006-06-20 06:53:54.000000000 +0300
+++ LinuxBIOSv2_ad4/src/cpu/amd/model_gx2/cpubug.c 2006-07-21 10:50:39.000000000 +0300
@@ -351,7 +351,7 @@
{
msr_t msr;
int rev;
-
+#if 0 //GX3
msr = rdmsr(GLCP_CHIP_REVID);
rev = msr.lo & 0xff;
@@ -386,4 +386,6 @@
bug118253();
disablememoryreadorder();
printk_debug("Done cpubug fixes \n");
+#endif
+
}
diff -r -b -B -u LinuxBIOSv2/src/cpu/amd/model_gx2/cpureginit.c LinuxBIOSv2_ad4/src/cpu/amd/model_gx2/cpureginit.c
--- LinuxBIOSv2/src/cpu/amd/model_gx2/cpureginit.c 2006-06-14 16:56:28.000000000 +0300
+++ LinuxBIOSv2_ad4/src/cpu/amd/model_gx2/cpureginit.c 2006-07-21 10:50:39.000000000 +0300
@@ -78,101 +78,34 @@
cpuRegInit (void){
int msrnum;
msr_t msr;
- /* Turn on BTM for early debug based on setup. */
- /*if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) {*/
- /*
- * The following is only for diagnostics mode; do not use for OLPC
- */
- if (0) {
- /* Set Diagnostic Mode */
- msrnum = CPU_GLD_MSR_DIAG;
- msr.hi = 0;
- msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET;
- wrmsr(msrnum, msr);
-
- /* Set up GLCP to grab BTM data.*/
- msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR*/
- msr.hi = 0x0;
- msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out,*/
- wrmsr(msrnum, msr); /* exchange it to anything else to prevent this*/
-
- /* ;Turn off debug clock*/
- msrnum = 0x04C000016; /* DBG_CLK_CTL*/
- msr.lo = 0x00; /* No clock*/
- msr.hi = 0x00;
- wrmsr(msrnum, msr);
- /* ;Set debug clock to CPU*/
- msrnum = 0x04C000016; /* DBG_CLK_CTL*/
- msr.lo = 0x01; /* CPU CLOCK*/
- msr.hi = 0x00;
- wrmsr(msrnum, msr);
-
- /* ;Set fifo ctl to BTM bits wide*/
- msrnum = 0x04C00005E; /* FIFO_CTL*/
- msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit)*/
- wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0)*/
- /* Bit [19] sets it up in slow data mode.*/
-
- /* ;enable fifo loading - BTM sizing will constrain*/
- /* ; only valid BTM packets to load - this action should always be on*/
-
- msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo*/
- msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger*/
- msr.hi = 0x000000000; /* */
- wrmsr(msrnum, msr);
-
- /* ;start storing diag data in the fifo*/
- msrnum = 0x04C00005F; /* DIAG CTL*/
- msr.lo = 0x080000000; /* enable actions*/
- msr.hi = 0x000000000;
- wrmsr(msrnum, msr);
-
- /* Set up delay on data lines, so that the hold time*/
- /* is 1 ns.*/
- msrnum = 0x04C00000D ; /* GLCP IO DELAY CONTROLS*/
- msr.lo = 0x082b5ad68;
- msr.hi = 0x080ad6b57; /* RGB delay = 0x07*/
- wrmsr(msrnum, msr);
-
- /* Set up DF to output diag information on DF pins.*/
- msrnum = DF_GLD_MSR_MASTER_CONF;
- msr.lo = 0x0220;
- msr.hi = 0;
- wrmsr(msrnum, msr);
-
- msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR*/
- msr.hi = 0x0;
- msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out,*/
- wrmsr(msrnum, msr);
- /* end of code for BTM */
- }
+ //GX3 suspend: what is desired?
/* Enable Suspend on Halt*/
- msrnum = CPU_XC_CONFIG;
+ /*msrnum = CPU_XC_CONFIG;
msr = rdmsr(msrnum);
msr.lo |= XC_CONFIG_SUSP_ON_HLT;
- wrmsr(msrnum, msr);
+ wrmsr(msrnum, msr);*/
/* ENable SUSP and allow TSC to run in Suspend */
/* to keep speed detection happy*/
- msrnum = CPU_BC_CONF_0;
+ /*msrnum = CPU_BC_CONF_0;
msr = rdmsr(msrnum);
msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
- wrmsr(msrnum, msr);
+ wrmsr(msrnum, msr);*/
/* Setup throttling to proper mode if it is ever enabled.*/
msrnum = 0x04C00001E;
msr.hi = 0x000000000;
msr.lo = 0x00000603C;
- wrmsr(msrnum, msr);
+ wrmsr(msrnum, msr); // GX3 OK +/-
/* Only do this if we are building for 5535*/
/* */
/* FooGlue Setup*/
/* */
-#if 1
+#if 0
/* Enable CIS mode B in FooGlue*/
msrnum = MSR_FG + 0x10;
msr = rdmsr(msrnum);
@@ -184,10 +117,13 @@
/* */
/* Disable DOT PLL. Graphics init will enable it if needed.*/
/* */
- msrnum = GLCP_DOTPLL;
+
+// GX3: Disable DOT PLL? No. Lets tick.
+
+/* msrnum = GLCP_DOTPLL;
msr = rdmsr(msrnum);
msr.lo |= DOTPPL_LOWER_PD_SET;
- wrmsr(msrnum, msr);
+ wrmsr(msrnum, msr); */
/* */
/* Enable RSDC*/
@@ -195,7 +131,7 @@
msrnum = 0x1301 ;
msr = rdmsr(msrnum);
msr.lo |= 0x08;
- wrmsr(msrnum, msr);
+ wrmsr(msrnum, msr); //GX3 OK
/* */
@@ -211,7 +147,10 @@
/* Enable BTB*/
/* */
/* I hate to put this check here but it doesn't really work in cpubug.asm*/
- msrnum = MSR_GLCP+0x17;
+
+//GX3: BTB is enabled by default
+
+/* msrnum = MSR_GLCP+0x17;
msr = rdmsr(msrnum);
if (msr.lo >= CPU_REV_2_1){
msrnum = CPU_PF_BTB_CONF;
@@ -220,17 +159,25 @@
wrmsr(msrnum, msr);
}
+ */
+
/* */
/* FPU impercise exceptions bit*/
/* */
/*if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) {*/
- {
+
+
+
+// GX3: FPU impercise exceptions bit - what's that?
+/* {
msrnum = CPU_FPU_MSR_MODE;
msr = rdmsr(msrnum);
msr.lo |= FPU_IE_SET;
wrmsr(msrnum, msr);
}
+ */
+
#if 0
/* */
/* Cache Overides*/
diff -r -b -B -u LinuxBIOSv2/src/cpu/amd/model_gx2/model_gx2_init.c LinuxBIOSv2_ad4/src/cpu/amd/model_gx2/model_gx2_init.c
--- LinuxBIOSv2/src/cpu/amd/model_gx2/model_gx2_init.c 2006-05-02 06:07:11.000000000 +0300
+++ LinuxBIOSv2_ad4/src/cpu/amd/model_gx2/model_gx2_init.c 2006-07-21 10:50:39.000000000 +0300
@@ -37,7 +37,7 @@
};
static struct cpu_device_id cpu_table[] = {
- { X86_VENDOR_NSC, 0x0552 },
+ { X86_VENDOR_NSC, 0x05A2 },
{ 0, 0 },
};
diff -r -b -B -u LinuxBIOSv2/src/include/cpu/amd/gx2def.h LinuxBIOSv2_ad4/src/include/cpu/amd/gx2def.h
--- LinuxBIOSv2/src/include/cpu/amd/gx2def.h 2006-06-11 01:57:15.000000000 +0300
+++ LinuxBIOSv2_ad4/src/include/cpu/amd/gx2def.h 2006-07-21 11:20:21.000000000 +0300
@@ -60,32 +60,35 @@
/* port5 - FG*/
+/* start GX3 def, differences are marked with GX3 comment */
+
#define GL0_GLIU0 0
#define GL0_MC 1
#define GL0_GLIU1 2
#define GL0_CPU 3
#define GL0_VG 4
#define GL0_GP 5
-#define GL0_DF 6
+//#define GL0_DF 6 //GX3 no such thing as VP port
#define GL1_GLIU0 1
+//GX3 VP port
+#define GL1_DF 2
#define GL1_GLCP 3
#define GL1_PCI 4
-#define GL1_FG 5
#define GL1_VIP 5
#define GL1_AES 6
#define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx - To get on GeodeLink one bit has to be set */
#define MSR_MC (GL0_MC << 29) /* 2000xxxx */
#define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */
-#define MSR_CPU (GL0_CPU << 29) /* 6000xxxx - this is not used for BIOS since code executing on CPU doesn't need to be routed*/
+#define MSR_CPU (GL0_CPU << 32) /* 0000xxxx - this is not used for BIOS */ //GX3
#define MSR_VG (GL0_VG << 29) /* 8000xxxx */
#define MSR_GP (GL0_GP << 29) /* A000xxxx */
-#define MSR_DF (GL0_DF << 29) /* C000xxxx */
+//#define MSR_DF (GL0_DF << 29) /* C000xxxx */ //GX3 no such thing
#define MSR_GLCP (GL1_GLCP << 26) + MSR_GLIU1 /* 4C00xxxx */
#define MSR_PCI (GL1_PCI << 26) + MSR_GLIU1 /* 5000xxxx */
-#define MSR_FG (GL1_FG << 26) + MSR_GLIU1 /* 5400xxxx */
+//#define MSR_FG (GL1_FG << 26) + MSR_GLIU1 /* 5400xxxx */ //GX3: no such thing
#define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */
#define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */
/* South Bridge*/
@@ -313,13 +316,13 @@
/**/
/* DF GLIU0 port6*/
/**/
-
+/*
#define DF_GLD_MSR_CAP (MSR_DF + 0x2000)
#define DF_GLD_MSR_MASTER_CONF (MSR_DF + 0x2001)
#define DF_LOWER_LCD_SHIFT 6
#define DF_GLD_MSR_PM (MSR_DF + 0x2004)
-
+*/
/**/
/* GeodeLink Control Processor GLIU1 port3*/
@@ -415,7 +418,7 @@
#define GLPCI_RC_LOWER_WC_SET (1<<4)
#define GLPCI_RC_LOWER_WP_SET (1<<2)
#define GLPCI_RC_LOWER_CD_SET (1<<0)
-#define GLPCI_ExtMSR (MSR_PCI + 0x201E)
+#define GLPCI_EXT_MSR (MSR_PCI + 0x201E)
#define GLPCI_SPARE (MSR_PCI + 0x201F)
#define GLPCI_SPARE_LOWER_AILTO_SET (1<<6)
#define GLPCI_SPARE_LOWER_PPD_SET (1<<5)
@@ -429,9 +432,10 @@
/**/
/* FooGlue GLIU1 port 5*/
/**/
+/* GX3 not needed?
#define FG_GLD_MSR_CAP (MSR_FG + 0x2000)
#define FG_GLD_MSR_PM (MSR_FG + 0x2004)
-
+*/
/* VIP GLIU1 port 5*/
/* */
#define VIP_GLD_MSR_CAP (MSR_VIP + 0x2000)
@@ -856,7 +860,7 @@
/* LBAR IO + MEMORY MAP*/
/* */
#define SMBUS_BASE ( 0x6000)
-#define GPIO_BASE ( 0x6100)
+#define GPIO_BASE ( 0xF000) /* GX3 */
#define MFGPT_BASE ( 0x6200)
#define IRQMAP_BASE ( 0x6300)
#define PMLogic_BASE ( 0x9D00)
diff -r -b -B -u LinuxBIOSv2/src/mainboard/olpc/rev_a/auto.c LinuxBIOSv2_ad4/src/mainboard/olpc/rev_a/auto.c
--- LinuxBIOSv2/src/mainboard/olpc/rev_a/auto.c 2006-06-11 01:57:15.000000000 +0300
+++ LinuxBIOSv2_ad4/src/mainboard/olpc/rev_a/auto.c 2006-07-21 11:29:23.000000000 +0300
@@ -9,12 +9,12 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+//#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/gx2def.h>
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+//#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
@@ -65,6 +66,8 @@
msr_t msr;
unsigned char module_banks, val;
+
+#if 0 //GX3
msr = rdmsr(MC_CF07_DATA);
/* get module banks (sides) per dimm, SPD byte 5 */
@@ -102,12 +105,19 @@
msr.lo = 0x00003000;
wrmsr(MC_CF07_DATA, msr);
+#endif
+
+ msr.hi = 0x00005012;
+ msr.lo = 0x05000040;
+
+ wrmsr(MC_CF07_DATA, msr); //GX3
+
/* timing and mode ... */
- msr = rdmsr(0x20000019);
+ //msr = rdmsr(0x20000019);
/* per standard bios settings */
-
+/*
msr.hi = 0x18000108;
msr.lo =
(6<<28) | // cas_lat
@@ -119,12 +129,12 @@
(2<<6)| // dplwr
(2<<4)| // dplrd
(3); // dal
- /* the msr value reported by quanta is very, very different.
+ * the msr value reported by quanta is very, very different.
* we will go with that value for now.
- */
- msr.lo = 0x286332a3;
-
- wrmsr(0x20000019, msr);
+ *
+ //msr.lo = 0x286332a3;
+*/
+ //wrmsr(0x20000019, msr); //GX3
}
@@ -156,25 +166,28 @@
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
};
- SystemPreInit();
- msr_init();
+ SystemPreInit(); //GX3 OK
+
+ msr_init(); //GX3 OK
- cs5536_early_setup();
+ cs5536_early_setup(); //GX3 OK
/* NOTE: must do this AFTER the early_setup!
* it is counting on some early MSR setup
* for cs5536
*/
- cs5536_setup_onchipuart();
- uart_init();
- console_init();
+ cs5536_setup_onchipuart(); //GX3 OK
+
+ uart_init(); //GX3 OK
+ console_init(); //GX3 OK
+
+ pll_reset(); //GX3 OK
- pll_reset();
+ cpuRegInit(); //GX3 OK
- cpuRegInit();
print_err("done cpuRegInit\n");
- sdram_initialize(1, memctrl);
+ sdram_initialize(1, memctrl); //GX3 OK almost
/* Check all of memory */
//ram_check(0x00000000, 640*1024);
diff -r -b -B -u LinuxBIOSv2/src/mainboard/olpc/rev_a/Options.lb LinuxBIOSv2_ad4/src/mainboard/olpc/rev_a/Options.lb
--- LinuxBIOSv2/src/mainboard/olpc/rev_a/Options.lb 2006-05-18 06:07:16.000000000 +0300
+++ LinuxBIOSv2_ad4/src/mainboard/olpc/rev_a/Options.lb 2006-07-21 10:50:39.000000000 +0300
@@ -112,8 +112,8 @@
## The default compiler
##
default CROSS_COMPILE=""
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CROSS_COMPILE)gcc-3.4 -m32"
+default HOSTCC="gcc-3.4"
##
## The Serial Console
diff -r -b -B -u LinuxBIOSv2/src/northbridge/amd/gx2/northbridgeinit.c LinuxBIOSv2_ad4/src/northbridge/amd/gx2/northbridgeinit.c
--- LinuxBIOSv2/src/northbridge/amd/gx2/northbridgeinit.c 2006-06-20 06:53:54.000000000 +0300
+++ LinuxBIOSv2_ad4/src/northbridge/amd/gx2/northbridgeinit.c 2006-07-21 10:50:39.000000000 +0300
@@ -59,10 +59,10 @@
{GLIU1_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}},
{VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163*/
{GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}},
- {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}},
+ /*{DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}},*/ //GX3
{GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}},
{GLPCI_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}},
- {FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* Always on*/
+ /*{FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, */ /* Always on*/ //GX3
{0xffffffff, {0xffffffff, 0xffffffff}},
};
/* All On*/
@@ -72,10 +72,10 @@
{GLIU1_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
{VG_GLD_MSR_PM, {.hi=0x00, .lo=0x00}},
{GP_GLD_MSR_PM, {.hi=0x00,.lo=0x000000001}},
- {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
+ /*{DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, */ //GX3
{GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
{GLPCI_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
- {FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}},
+ /*{FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, */ //GX3
{0xffffffff, {0xffffffff, 0xffffffff}},
};
@@ -83,7 +83,7 @@
struct msrinit ClockGatingPerformance[] = {
{VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163*/
{GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}},
- {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}},
+ /*{DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}}, */ //GX3
{GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}},
{0xffffffff, {0xffffffff, 0xffffffff}},
};
@@ -92,7 +92,7 @@
/* */
struct msrinit GeodeLinkPriorityTable [] = {
{CPU_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0220}}, /* CPU Priority.*/
- {DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority.*/
+ /*{DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}},*/ /* DF Priority.*/ //GX3
{VG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0720}}, /* VG Primary and Secondary Priority.*/
{GP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0010}}, /* Graphics Priority.*/
{GLPCI_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0027}}, /* GLPCI Priority + PID*/
diff -r -b -B -u LinuxBIOSv2/src/northbridge/amd/gx2/pll_reset.c LinuxBIOSv2_ad4/src/northbridge/amd/gx2/pll_reset.c
--- LinuxBIOSv2/src/northbridge/amd/gx2/pll_reset.c 2006-05-12 21:42:34.000000000 +0300
+++ LinuxBIOSv2_ad4/src/northbridge/amd/gx2/pll_reset.c 2006-07-21 10:50:39.000000000 +0300
@@ -110,7 +110,43 @@
}
#endif
-#define USE_GOODRICH_VERSION 1
+
+#if 1
+//PLLCHECK_COMPLETED is the "we've already done this" flag
+#define PLLCHECK_COMPLETED (1 << RSTPLL_LOWER_SWFLAGS_SHIFT)
+#define POST_CODE(x) outb(0x80, x)
+
+static void pll_reset(void)
+{
+ msr_t msrGlcpSysRstpll;
+ unsigned MDIV_VDIV_FBDIV;
+ unsigned SyncBits; // store the sync bits in up ebx
+
+ // clear the Bypass bit
+
+ // If the straps say we are in bypass and the syspll is not AND there are no software
+ // bits set then FS2 or something set up the PLL and we should not change it.
+
+ msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
+ msrGlcpSysRstpll.lo &= 0x80000000;
+
+ // If the "we've already been here" flag is set, don't reconfigure the pll
+ if ( !(msrGlcpSysRstpll.lo) )
+ { // we haven't configured the PLL; do it now
+
+ // Store PCI33(0)/66(1), SDR(0)/DDR(1), and CRT(0)/TFT(1) in upper esi to get to the
+ // correct Strap Table.
+ POST_CODE(0x77);
+ msrGlcpSysRstpll.hi = 0x000002CB;
+ msrGlcpSysRstpll.lo = 0x80DE0081;
+ wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
+ }
+
+}
+#endif
+
+
+#define USE_GOODRICH_VERSION 0
#if USE_GOODRICH_VERSION
///////////////////////////////////////////////////////////////////////////////
@@ -248,7 +284,7 @@
#else // #if USE_GOODRICH_VERSION
-static void pll_reset(void)
+static void pll_reset_good(void)
{
msr_t msr;
unsigned int sysref, spll_raw, cpu_core, gliu;
diff -r -b -B -u LinuxBIOSv2/src/northbridge/amd/gx2/raminit.c LinuxBIOSv2_ad4/src/northbridge/amd/gx2/raminit.c
--- LinuxBIOSv2/src/northbridge/amd/gx2/raminit.c 2006-05-02 06:07:11.000000000 +0300
+++ LinuxBIOSv2_ad4/src/northbridge/amd/gx2/raminit.c 2006-07-21 10:50:39.000000000 +0300
@@ -1,9 +1,13 @@
#include <cpu/amd/gx2def.h>
+#if 0
static void sdram_set_registers(const struct mem_controller *ctrl)
{
}
+#endif
+
+
/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
* Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
@@ -11,40 +15,59 @@
int i;
msr_t msr;
- /* 2. clock gating for PMode */
- msr = rdmsr(0x20002004);
- msr.lo &= ~0x04;
- msr.lo |= 0x01;
- wrmsr(0x20002004, msr);
- /* undocmented bits in GX, in LX there are
- * 8 bits in PM1_UP_DLY */
- msr = rdmsr(0x2000001a);
- msr.lo = 0x0101;
- wrmsr(0x2000001a, msr);
- //print_debug("sdram_enable step 2\r\n");
-
- /* 3. release CKE mask to enable CKE */
- msr = rdmsr(0x2000001d);
- msr.lo &= ~(0x03 << 8);
- wrmsr(0x2000201d, msr);
+ /* DRAM initialization sequence according to the documentation:
+ * 1) Initialize the following GLMC registers/bits based on Serial Presence Detect (SPD) values:
+ * â MSR 20000018h except REF_INT bits [23:8]
+ * â MSR 20000019h
+ */
+
+ // This is done by sdram_set_spd_registers()
+ /*WR_MSR MC_CF07_DATA, DIMMCONFIG, 0x05000040
+
+ ;WR_MSR MC_CF07_DATA, DIMMCONFIG, 0x00000040 ; MSR 20000018h except REF_INT bits [23:8]. REF_STAG value from DOCS*/
+
+ msr.hi = 0x18000100;
+ msr.lo = 0x696332A3;
+ wrmsr(MC_CF8F_DATA, msr);
+
+ /* 2) Initialize the following GLMC registers:
+ * â MSR 2000001Ah[15:8] = C8h
+ * â MSR 20002004h[2] = 0, [0] = 1
+ */
+ msr.hi = 0x00000000;
+ msr.lo = 0x130AD101;
+ wrmsr(MC_CF1017_DATA, msr);
+
+ msr.hi = 0x00000000;
+ msr.lo = 0x00000001;
+ wrmsr(MC_GLD_MSR_PM, msr);
+
+ /* 3) Release MASK_CKE[1:0] (MSR 2000001Dh[9:8] = 11) */
+
+ msr.hi = 0x00000000;
+ msr.lo = 0x00001000;
+ wrmsr(MC_CFCLK_DBUG, msr);
+
//print_debug("sdram_enable step 3\r\n");
/* 4. set and clear REF_TST 16 times, more shouldn't hurt
* why this is before EMRS and MRS ? */
+
for (i = 0; i < 19; i++) {
- msr = rdmsr(0x20000018);
+ msr = rdmsr(MC_CF07_DATA);
msr.lo |= (0x01 << 3);
- wrmsr(0x20000018, msr);
+ wrmsr(MC_CF07_DATA, msr);
msr.lo &= ~(0x01 << 3);
- wrmsr(0x20000018, msr);
+ wrmsr(MC_CF07_DATA, msr);
}
- //print_debug("sdram_enable step 4\r\n");
- /* 5. set refresh interval */
- msr = rdmsr(0x20000018);
- msr.lo &= ~(0xffff << 8);
- msr.lo |= (0x34 << 8);
- wrmsr(0x20000018, msr);
+
+ /* 5) Initialize REF_INT (MSR 20000018h[23:8]) to set refresh interval. */
+ msr.lo |= 0x2B00;
+ wrmsr(MC_CF07_DATA, msr);
+
+
+
/* set refresh staggering to 4 SDRAM clocks */
msr = rdmsr(0x20000018);
msr.lo &= ~(0x03 << 6);
@@ -52,30 +75,35 @@
wrmsr(0x20000018, msr);
//print_debug("sdram_enable step 5\r\n");
- /* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */
- msr = rdmsr(0x20000018);
+
+ /* 6) Perform load-mode with MSR_BA = 01 (MSR 200000018h[29:28] = 01)
+ * to initialize DIMM Extended Mode register.
+ * Load-mode is performed by setting/clearing PROG_DRAM (MSR 200000018h[0]).
+ */
msr.lo |= ((0x01 << 28) | 0x01);
- wrmsr(0x20000018, msr);
+ wrmsr(MC_CF07_DATA, msr);
+
msr.lo &= ~((0x01 << 28) | 0x01);
- wrmsr(0x20000018, msr);
- //print_debug("sdram_enable step 6\r\n");
+ wrmsr(MC_CF07_DATA, msr);
+
/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
* it is documented in LX datasheet */
/* load Mode Register by set and clear PROG_DRAM */
- msr = rdmsr(0x20000018);
+ msr = rdmsr(MC_CF07_DATA);
msr.lo |= ((0x01 << 27) | 0x01);
- wrmsr(0x20000018, msr);
+ wrmsr(MC_CF07_DATA, msr);
msr.lo &= ~((0x01 << 27) | 0x01);
- wrmsr(0x20000018, msr);
+ wrmsr(MC_CF07_DATA, msr);
//print_debug("sdram_enable step 7\r\n");
+
/* 8. load Mode Register by set and clear PROG_DRAM */
- msr = rdmsr(0x20000018);
+ msr = rdmsr(MC_CF07_DATA);
msr.lo |= 0x01;
- wrmsr(0x20000018, msr);
+ wrmsr(MC_CF07_DATA, msr);
msr.lo &= ~0x01;
- wrmsr(0x20000018, msr);
+ wrmsr(MC_CF07_DATA, msr);
//print_debug("sdram_enable step 8\r\n");
/* wait 200 SDCLKs */
@@ -83,10 +111,10 @@
outb(0xaa, 0x80);
/* load RDSYNC */
- msr = rdmsr(0x2000001f);
+ /*msr = rdmsr(0x2000001f);
msr.hi = 0x000ff310;
msr.lo = 0x00000000;
- wrmsr(0x2000001f, msr);
+ wrmsr(0x2000001f, msr);*/
/* set delay control */
msr = rdmsr(0x4c00000f);
@@ -94,6 +122,9 @@
msr.lo = 0x8ea0ad6a;
wrmsr(0x4c00000f, msr);
+
+ print_debug("DRAM controller init done.\r\n");
+
/* DRAM working now?? */
}
diff -r -b -B -u LinuxBIOSv2/src/sdram/generic_sdram.c LinuxBIOSv2_ad4/src/sdram/generic_sdram.c
--- LinuxBIOSv2/src/sdram/generic_sdram.c 2005-12-02 23:52:30.000000000 +0200
+++ LinuxBIOSv2_ad4/src/sdram/generic_sdram.c 2006-07-21 10:50:39.000000000 +0300
@@ -28,7 +28,10 @@
#endif
{
int i;
+
+#if 0
/* Set the registers we can set once to reasonable values */
+
for(i = 0; i < controllers; i++) {
print_debug_sdram_8("Ram1.",i);
@@ -38,6 +41,8 @@
sdram_set_registers(ctrl + i);
#endif
}
+#endif
+
/* Now setup those things we can auto detect */
for(i = 0; i < controllers; i++) {
diff -r -b -B -u LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_setup.c LinuxBIOSv2_ad4/src/southbridge/amd/cs5536/cs5536_early_setup.c
--- LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_setup.c 2006-06-11 01:57:15.000000000 +0300
+++ LinuxBIOSv2_ad4/src/southbridge/amd/cs5536/cs5536_early_setup.c 2006-07-21 11:40:01.000000000 +0300
@@ -30,7 +30,9 @@
} else {
msr.hi = CS5536_DEV_NUM << ((CS5536_GLINK_PORT_NUM - 5) * 8);
}
- wrmsr(0x5000201e, msr);
+
+ msr.lo = 0x00000F00;
+ wrmsr(GLPCI_EXT_MSR, msr);
}
static void cs5536_setup_idsel(void)
@@ -57,16 +59,18 @@
{
msr_t msr;
+ // NB!!!!! __builtin_wrmsr(low,high)
+
/* setup LBAR for SMBus controller */
- __builtin_wrmsr(0x5140000b, 0x00006000, 0x0000f001);
+ //__builtin_wrmsr(0x5140000b, 0x00006000, 0x0000f001);
/* setup LBAR for GPIO */
- __builtin_wrmsr(0x5140000c, 0x00006100, 0x0000f001);
+ __builtin_wrmsr(MDD_LBAR_GPIO, GPIO_BASE, GPIO_BASE + 1 );
/* setup LBAR for MFGPT */
- __builtin_wrmsr(0x5140000d, 0x00006200, 0x0000f001);
+ //__builtin_wrmsr(0x5140000d, 0x00006200, 0x0000f001);
/* setup LBAR for ACPI */
- __builtin_wrmsr(0x5140000e, 0x00009c00, 0x0000f001);
+ //__builtin_wrmsr(0x5140000e, 0x00009c00, 0x0000f001);
/* setup LBAR for PM Support */
- __builtin_wrmsr(0x5140000f, 0x00009d00, 0x0000f001);
+ //__builtin_wrmsr(0x5140000f, 0x00009d00, 0x0000f001);
}
static void cs5536_setup_power_bottun(void)
@@ -99,39 +103,47 @@
{
uint32_t val;
+
+ /* GX3: Enable GPIO pins for UART2 */
+ outl(0x00000010, GPIOL_OUT_AUX1_SELECT);
+ outl(0x00000010, GPIOL_OUTPUT_ENABLE);
+ outl(0x00000008, GPIOL_IN_AUX1_SELECT);
+ outl(0x00000008, GPIOL_INPUT_ENABLE);
+
+
/* setup GPIO pins 14/15 for SDA/SCL */
- val = (1<<14 | 1<<15);
+ //val = (1<<14 | 1<<15);
/* Output Enable */
- outl(0x3fffc000, 0x6100 + 0x04);
+ //outl(0x3fffc000, 0x6100 + 0x04);
//outl(val, 0x6100 + 0x04);
/* Output AUX1 */
- outl(0x3fffc000, 0x6100 + 0x10);
+ //outl(0x3fffc000, 0x6100 + 0x10);
//outl(val, 0x6100 + 0x10);
/* Input Enable */
//outl(0x0f5af0a5, 0x6100 + 0x20);
- outl(0x3fffc000, 0x6100 + 0x20);
+ //outl(0x3fffc000, 0x6100 + 0x20);
//outl(val, 0x6100 + 0x20);
/* Input AUX1 */
//outl(0x3ffbc004, 0x6100 + 0x34);
- outl(0x3fffc000, 0x6100 + 0x34);
+ //outl(0x3fffc000, 0x6100 + 0x34);
//outl(val, 0x6100 + 0x34);
#if 0
/* changes proposed by Ollie; we will test this later. */
/* setup GPIO pins 14/15 for SDA/SCL */
- val = GPIOL_15_SET | GPIOL_14_SET;
+ //val = GPIOL_15_SET | GPIOL_14_SET;
/* Output Enable */
//outl(0x3fffc000, 0x6100 + 0x04);
- outl(val, 0x6100 + 0x04);
+ //outl(val, 0x6100 + 0x04);
/* Output AUX1 */
//outl(0x3fffc000, 0x6100 + 0x10);
- outl(val, 0x6100 + 0x10);
+ //outl(val, 0x6100 + 0x10);
/* Input Enable */
//outl(0x3fffc000, 0x6100 + 0x20);
- outl(val, 0x6100 + 0x20);
+ //outl(val, 0x6100 + 0x20);
/* Input AUX1 */
//outl(0x3fffc000, 0x6100 + 0x34);
- outl(val, 0x6100 + 0x34);
+ //outl(val, 0x6100 + 0x34);
#endif
}
@@ -168,7 +180,7 @@
msr.lo |= 0x10;
__builtin_wrmsr(0x51000010, msr.lo, msr.hi);
//Only do this if we are building for 5536
- __builtin_wrmsr(0x54002010, 0x00000002, 0x00000000);
+// __builtin_wrmsr(0x54002010, 0x00000002, 0x00000000); //GX3: no such register
}
static void dummy(void)
@@ -179,6 +191,8 @@
static int cs5536_setup_onchipuart(void)
{
unsigned long m;
+ unsigned char n;
+
/*
* 1. Eanble GPIO 8 to OUT_AUX1, 9 to IN_AUX1
* GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34
@@ -189,42 +203,76 @@
* 4. IRQ routing on IRQ Mapper
* MSR 0x51400021 bit [27:24]
*/
+
+
+ // GX3: my board has UART2 wired up ;)
+
msr_t msr;
+
+ // enable UART2 as COM1
+ msr = rdmsr(MDD_LEG_IO);
+ msr.lo |= 0x700000;
+ wrmsr(MDD_LEG_IO, msr);
+
+ // reset UART2
+ msr = rdmsr(MDD_UART2_CONF);
+ msr.lo = 1;
+ wrmsr(MDD_UART2_CONF, msr);
+
+ // clear reset UART2
+ msr.lo = 0;
+ wrmsr(MDD_UART2_CONF, msr);
+
+ // enable UART2
msr.lo = 2;
- msr.hi = 0;
- /* This enables COM2, but that should be done elsewhere
- wrmsr(0x5140003e, msr);
- */
+ wrmsr(MDD_UART2_CONF, msr);
+
+
+ // Set DLAB
+ n = 0x80;
+ outb(n, TTYS0_BASE + 3);
+
+ // Baud rate divisor
+ n = 0x01;
+ outb(n, TTYS0_BASE);
+ // Line mode (8N1)
+ n = 0x03;
+ outb(n, TTYS0_BASE + 3);
- /* enable COM1 */
- wrmsr(0x5140003a, msr);
- /* GPIO8 - UART1_TX */
- /* Set: Output Enable (0x4) */
+ // Clear DTR & RTS
+ n = 0x00;
+ outb(n, TTYS0_BASE + 4);
+
+
+ /* enable COM1 *
+ //wrmsr(0x5140003a, msr);
+ * GPIO8 - UART1_TX *
+ * Set: Output Enable (0x4)
m = inl(GPIOL_OUTPUT_ENABLE);
m |= GPIOL_8_SET;
m &= ~GPIOL_8_CLEAR;
- outl(m,GPIOL_OUTPUT_ENABLE);
- /* Set: OUTAUX1 Select (0x10) */
+ outl(m,GPIOL_OUTPUT_ENABLE);*
+ * Set: OUTAUX1 Select (0x10) *
m = inl(GPIOL_OUT_AUX1_SELECT);
m |= GPIOL_8_SET;
m &= ~GPIOL_8_CLEAR;
outl(m,GPIOL_OUT_AUX1_SELECT);
- /* Set: Pull Up (0x18) */
+ * Set: Pull Up (0x18) *
m = inl(GPIOL_PULLUP_ENABLE);
m |= GPIOL_8_SET;
m &= ~GPIOL_8_CLEAR;
- /* GPIO9 - UART1_RX */
- /* Set: Pull Up (0x18) */
+ * GPIO9 - UART1_RX *
+ * Set: Pull Up (0x18) *
m |= GPIOL_9_SET;
m &= ~GPIOL_9_CLEAR;
outl(m,GPIOL_PULLUP_ENABLE);
- /* Set: Input Enable (0x20) */
+ * Set: Input Enable (0x20) *
m = inl(GPIOL_INPUT_ENABLE);
m |= GPIOL_9_SET;
m &= ~GPIOL_9_CLEAR;
outl(m,GPIOL_INPUT_ENABLE);
- /* Set: INAUX1 Select (0x34) */
+ * Set: INAUX1 Select (0x34) *
m = inl(GPIOL_IN_AUX1_SELECT);
m |= GPIOL_9_SET;
m &= ~GPIOL_9_CLEAR;
@@ -232,7 +280,7 @@
msr = rdmsr(MDD_LEG_IO);
msr.lo |= 0x7 << 16;
- wrmsr(MDD_LEG_IO,msr);
+ wrmsr(MDD_LEG_IO,msr);*/
}
/* note: you can't do prints in here in most cases,
@@ -243,24 +291,30 @@
{
msr_t msr;
- cs5536_setup_extmsr();
+ cs5536_setup_extmsr(); //GX3 OK
msr = rdmsr(GLCP_SYS_RSTPLL);
- if (msr.lo & (0x3f << 26)) {
+ if (0){// msr.lo & (0x3f << 26)) {
/* PLL is already set and we are reboot from PLL reset */
//print_debug("reboot from BIOS reset\n\r");
return;
}
//print_debug("Setup idsel\r\n");
- cs5536_setup_idsel();
+ cs5536_setup_idsel(); //GX3 OK
+
//print_debug("Setup iobase\r\n");
- cs5536_usb_swapsif();
- cs5536_setup_iobase();
+// cs5536_usb_swapsif(); //GX3 why?
+
+ cs5536_setup_iobase(); //GX3 OK
+
//print_debug("Setup gpio\r\n");
- cs5536_setup_gpio();
+ cs5536_setup_gpio(); //GX3 OK
+
//print_debug("Setup cis_mode\r\n");
- cs5536_setup_cis_mode();
+ cs5536_setup_cis_mode(); //GX3 OK
+
//print_debug("Setup smbus\r\n");
- cs5536_enable_smbus();
+// cs5536_enable_smbus(); //GX3 not needed
+
dummy();
}
diff -r -b -B -u LinuxBIOSv2/targets/olpc/rev_a/Config.lb LinuxBIOSv2_ad4/targets/olpc/rev_a/Config.lb
--- LinuxBIOSv2/targets/olpc/rev_a/Config.lb 2006-06-11 01:57:15.000000000 +0300
+++ LinuxBIOSv2_ad4/targets/olpc/rev_a/Config.lb 2006-07-21 10:50:39.000000000 +0300
@@ -3,9 +3,9 @@
target rev_a
mainboard olpc/rev_a
-# leave 64k for vsa
+# leave 128k for vsa
option CONFIG_COMPRESSED_ROM_STREAM=0
-option ROM_SIZE=1024*512-64*1024
+option ROM_SIZE=1024*256-128*1024
option FALLBACK_SIZE=ROM_SIZE
option DEFAULT_CONSOLE_LOGLEVEL = 11
--
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