This patch adds L2 cache initialization for Geode LX CPU.
Signed-off-by: Indrek Kruusa <[EMAIL PROTECTED]>
diff -u -r -b -B LinuxBIOSv2/src/cpu/amd/model_lx/model_lx_init.c LinuxBIOSv2_cp4/src/cpu/amd/model_lx/model_lx_init.c
--- LinuxBIOSv2/src/cpu/amd/model_lx/model_lx_init.c 2006-07-28 19:06:16.000000000 +0300
+++ LinuxBIOSv2_cp4/src/cpu/amd/model_lx/model_lx_init.c 2006-08-01 20:27:17.000000000 +0300
@@ -5,7 +5,7 @@
#include <cpu/cpu.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/cache.h>
-
+#include <cpu/amd/lxdef.h>
static void vsm_end_post_smi(void)
{
@@ -19,9 +19,37 @@
static void model_lx_init(device_t dev)
{
+
+ msr_t msr;
+
printk_debug("model_lx_init\n");
/* Turn on caching if we haven't already */
+
+ /* Instruction Memory Configuration register
+ * set EBE bit, required when L2 cache is enabled
+ */
+ msr = rdmsr(CPU_IM_CONFIG);
+ msr.lo |= 0x400;
+ wrmsr(CPU_IM_CONFIG, msr);
+
+ /* Data Memory Subsystem Configuration register
+ * set EVCTONRPL bit, required when L2 cache is enabled in victim mode
+ */
+ msr = rdmsr(CPU_DM_CONFIG0);
+ msr.lo |= 0x4000;
+ wrmsr(CPU_DM_CONFIG0, msr);
+
+ /* invalidate L2 cache */
+ msr.hi = 0x00;
+ msr.lo = 0x10;
+ wrmsr(L2_CONFIG_MSR, msr);
+
+ /* Enable L2 cache */
+ msr.hi = 0x00;
+ msr.lo = 0x0f;
+ wrmsr(L2_CONFIG_MSR, msr);
+
x86_enable_cache();
/* Enable the local cpu apics */
--
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