On Thu, Mar 29, 2007 at 06:26:16AM -0400, Corey Osgood wrote: > I'm still not entirely convinced that the previous version was flawed, > but this one has more features, and covers some of what Uwe had marked > as TODO anyways, with more that I'll fix up later.
My guess is that the problem was that the
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
was not done explicitly before. I think I'll be able to test some code
this evening...
I'd prefer a less invasive patch, though. We should leave superio.c as
is for now, until we can really test that part of the code.
Let's just fix it8705f_early_serial.c for now.
> +/*----------------------------------------------------------------------------------
> + * Function: pnp_enter_conf_state
> + * Parameters: dev - high 8 bits = Super I/O port
> + * Return Value: None
> + * Description: Enable access to the IT8705F's configuration registers.
> + */
Please don't copy these code comments. We should use Doxygen-style
comments for all new code we write (or "normal" code comments).
> +static inline void pnp_enter_conf_state(device_t dev) {
> + /* Port 0x2e is constant, no matter what */
Nope, I think for the IT8705F it can be 0x4e, too. The special address
used for entering MB PnP mode is always 0x2e, though (if I'm reading the
data sheet correctly). However, this is not the same as the configuration
port which will be used later...
> +static void pnp_exit_conf_state(device_t dev) {
> + outb(0xaa, 0x2e);
> }
I'm not sure this is correct. The datasheet suggests that the current
version is correct. Is this a copy-n-paste error from the other Super I/O?
> + pnp_enter_conf_state(dev);
> + pnp_set_logical_device(dev);
> + pnp_set_enable(dev, 0);
> + pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
> + pnp_set_enable(dev, 1);
> + pnp_exit_conf_state(dev);
Ok, this looks good. Let's do it this way, if it's enough to make the
Super I/O work...
See attached (untested, yet) patch for a new version which fixes several
issues I was doing wrong in the ITE Super I/Os (the others need fixing,
too; I'll post patches).
Does this patch work on your board?
Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
Lots of improvements for the IT8705F Super I/O.
* Renamed variables and defines to not have 'IT8705F' in the name, if it's
not necessary (makes it easier to copy the code to other Super I/Os).
* Correctly handle the different configuration port configs (0x2e vs. 0x4e).
* Only enable the user-selected serial port (no other devices) in
it8705f_enable_serial().
Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Index: it8705f_early_serial.c
===================================================================
--- it8705f_early_serial.c (Revision 2573)
+++ it8705f_early_serial.c (Arbeitskopie)
@@ -1,7 +1,8 @@
/*
* This file is part of the LinuxBIOS project.
*
- * Copyright (C) 2006 Uwe Hermann <[EMAIL PROTECTED]>
+ * Copyright (C) 2006-2007 Uwe Hermann <[EMAIL PROTECTED]>
+ * Copyright (C) 2007 Corey Osgood <[EMAIL PROTECTED]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -21,69 +22,101 @@
#include <arch/romcc_io.h>
#include "it8705f.h"
-/* The base address is 0x2e or 0x4e, depending on config bytes. */
-#define SIO_BASE 0x2e
-#define SIO_INDEX SIO_BASE
-#define SIO_DATA SIO_BASE+1
-
/* Global configuration registers. */
-#define IT8705F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
-#define IT8705F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
-#define IT8705F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
+#define CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
+#define CONFIG_REG_LDN 0x07 /* Logical Device Number. */
+#define CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
/* WTF? 0x23 and 0x24 are swapped here (when compared to other IT87xx). */
-#define IT8705F_CONFIG_REG_CLOCKSEL 0x24 /* Clock Selection, Flash I/F. */
-#define IT8705F_CONFIG_REG_SWSUSP 0x23 /* Software Suspend. */
+#define CONFIG_REG_CLOCKSEL 0x24 /* Clock Selection, Flash I/F. */
+#define CONFIG_REG_SWSUSP 0x23 /* Software Suspend. */
-#define IT8705F_CONFIGURATION_PORT 0x2e /* Write-only. */
+/**
+ * TODO
+ *
+ * The content of CONFIG_REG_LDN (index 0x07) must be set to the logical device
+ * number (LDN) the register belongs to, before you can access the register.
+ *
+ * @param ldn TODO
+ * @param index TODO
+ * @param value TODO
+ */
+static void sio_write(device_t dev, uint8_t ldn, uint8_t index, uint8_t value)
+{
+ unsigned int port = dev >> 8;
+ unsigned int addr = port;
+ unsigned int data = port + 1;
-/* The content of IT8705F_CONFIG_REG_LDN (index 0x07) must be set to the
- LDN the register belongs to, before you can access the register. */
-static void it8705f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
-{
- outb(IT8705F_CONFIG_REG_LDN, SIO_BASE);
- outb(ldn, SIO_DATA);
- outb(index, SIO_BASE);
- outb(value, SIO_DATA);
+ outb(CONFIG_REG_LDN, addr);
+ outb(ldn, data);
+ outb(index, addr);
+ outb(value, data);
}
-/* Enable the peripheral devices on the IT8705F Super I/O chip. */
-static void it8705f_enable_serial(device_t dev, unsigned iobase)
-{
- /* (1) Enter the configuration state (MB PnP mode). */
+/**
+ * Enter the configuration state (MB PnP mode) by writing a special sequence
+ * of four bytes to the special address 0x2e.
+ *
+ * Depending on above byte sequence, the configuration ports (addr/data) will
+ * be either 0x2e/0x2f or 0x4e/0x4f.
+ *
+ * For config ports 0x2e/0x2f use: 0x87 0x01 0x55 0x55.
+ * For config ports 0x4e/0x4f use: 0x87 0x01 0x55 0xaa.
+ *
+ * @param dev TODO
+ */
+static inline void pnp_enter_conf_state(device_t dev) {
+ uint8_t special_addr = 0x2e;
+ unsigned int port = dev >> 8;
- /* Perform MB PnP setup to put the SIO chip at 0x2e. */
- /* Base address 0x2e: 0x87 0x01 0x55 0x55. */
- /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
- outb(0x87, IT8705F_CONFIGURATION_PORT);
- outb(0x01, IT8705F_CONFIGURATION_PORT);
- outb(0x55, IT8705F_CONFIGURATION_PORT);
- outb(0x55, IT8705F_CONFIGURATION_PORT);
+ outb(0x87, special_addr);
+ outb(0x01, special_addr);
+ outb(0x55, special_addr);
+ if (port == 0x4e) {
+ outb(0xaa, special_addr);
+ } else {
+ outb(0x55, special_addr);
+ }
+}
- /* (2) Modify the data of configuration registers. */
+/**
+ * Exit the configuration state (MB PnP mode) by setting bit 1 of
+ * CONFIG_REG_CC.
+ *
+ * @param dev TODO
+ */
+static void pnp_exit_conf_state(device_t dev) {
+ sio_write(dev, 0x00, CONFIG_REG_CC, 0x02);
+}
+/**
+ * Enable the user-selected serial port.
+ *
+ * @param dev TODO
+ * @param iobase TODO
+ */
+static void it8705f_enable_serial(device_t dev, unsigned int iobase)
+{
/* Select the chip to configure (if there's more than one).
- Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
- If this register is not written, both chips are configured. */
- /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CONFIGSEL, 0x00); */
+ Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
+ If this register is not written, both chips are configured. */
+ // sio_write(0x00, CONFIG_REG_CONFIGSEL, 0x00);
- /* Enable all devices. */
- it8705f_sio_write(IT8705F_FDC, 0x30, 0x1); /* Floppy */
- it8705f_sio_write(IT8705F_SP1, 0x30, 0x1); /* Serial port 1 */
- it8705f_sio_write(IT8705F_SP2, 0x30, 0x1); /* Serial port 2 */
- it8705f_sio_write(IT8705F_PP, 0x30, 0x1); /* Parallel port */
- it8705f_sio_write(IT8705F_EC, 0x30, 0x1); /* Environment controller */
- it8705f_sio_write(IT8705F_GAME, 0x30, 0x1); /* GAME port */
- it8705f_sio_write(IT8705F_IR, 0x30, 0x1); /* Consumer IR */
- it8705f_sio_write(IT8705F_MIDI, 0x30, 0x1); /* MIDI port */
+ /* Enable the serial port(s). */
+ // sio_write(IT8705F_SP1, 0x30, 0x1); /* Serial port 1 */
+ // sio_write(IT8705F_SP2, 0x30, 0x1); /* Serial port 2 */
/* Select 24MHz CLKIN (set bit 0). */
- it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CLOCKSEL, 0x01);
+ // sio_write(0x00, CONFIG_REG_CLOCKSEL, 0x01);
/* Clear software suspend mode (clear bit 0). TODO: Needed? */
- /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_SWSUSP, 0x00); */
+ // sio_write(0x00, CONFIG_REG_SWSUSP, 0x00);
- /* (3) Exit the configuration state (MB PnP mode). */
- it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CC, 0x02);
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
}
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