Corey Osgood wrote:
> Corey Osgood wrote:
>> My email address is different in the headers, because I'll be losing my
>> Verizon email address soon, due to the Fairpoint takeover. Not sure if
>> the sign-off should be this email or that one, but they're both mine.
>>
>> This is the first patch for the Fintek F81705f for early serial support,
>> a second one will follow once I'm able to test the post-RAM port. I've
>> tested this on the Jetway J7F2WE1G, and it seems to work fine.
>>
>> Signed-off-by: Corey Osgood <[EMAIL PROTECTED]>
>>
>
> My bad, it's Fintek F71805f (the code is right, just not the email). I'm
> slightly dyslexic, and working on the it8705 didn't help.
>
> -Corey
>
No, actually it wasn't, I messed up the folder name when copying it over
to my clean checkout. Fixed patch attached.
Signed-off-by: Corey Osgood <[EMAIL PROTECTED]>
Index: src/superio/fintek/f71805f/f71805f.h
===================================================================
--- src/superio/fintek/f71805f/f71805f.h (revision 0)
+++ src/superio/fintek/f71805f/f71805f.h (revision 0)
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Corey Osgood <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Logical Device Numbers (LDN) */
+#define F71805F_FDC 0x00 /* Floppy */
+#define F71805F_SP1 0x01 /* UART1 */
+#define F71805F_SP2 0x02 /* UART2 */
+#define F71805F_PP 0x03 /* Parallel Port */
+#define F71805F_HWM 0x04 /* Hardware Monitor */
+#define F71805F_GPIO 0x06 /* General Purpose I/O (GPIO) */
+#define F71805F_PME 0x0A /* Power Management Events (PME) */
+/* All others reserved */
+
+/* Generic Registers */
+/* Not used yet, but may be in the future */
+#define F71805F_CHIP_ID1 0x20 /* Chip ID 1 of F71805 (Def: 0x04) */
+#define F71805F_CHIP_ID2 0x21 /* Chip ID 2 of F71805 (Def: 0x06) */
+#define F71805F_VENDOR_ID1 0x23 /* Vendor ID 1 of Fintek Devices */
+#define F71805F_VENDOR_ID2 0x24 /* Vendor ID 2 of Fintek Devices */
+#define F71805F_SOFTPD 0x25 /* Software Pull-Down Register */
+#define F71805F_IRQ_CTL 0x26 /* UART IRQ Sharing Register */
+#define F71805F_PWON_TRAP 0x27 /* Power On Trap Status Register */
+#define F71805F_FLASH_CTL 0x28 /* Flash Control Register */
+#define F71805F_VFAULT_CTL 0x29 /* Voltage Fault Enable Register */
Index: src/superio/fintek/f71805f/chip.h
===================================================================
--- src/superio/fintek/f71805f/chip.h (revision 0)
+++ src/superio/fintek/f71805f/chip.h (revision 0)
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Corey Osgood <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+struct chip_operations;
+extern struct chip_operations superio_fintek_f71805f_ops;
+
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+struct superio_fintek_f71805f_config {
+ struct uart8250 com1, com2;
+};
Index: src/superio/fintek/f71805f/f71805f_early_serial.c
===================================================================
--- src/superio/fintek/f71805f/f71805f_early_serial.c (revision 0)
+++ src/superio/fintek/f71805f/f71805f_early_serial.c (revision 0)
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Corey Osgood <[EMAIL PROTECTED]>
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Ported from the SMSC LPC47B272 driver */
+
+/* Pre-RAM driver for Fintek F71805F Super I/O chip. */
+
+
+#include <arch/romcc_io.h>
+#include "f71805f.h"
+
+static inline void pnp_enter_conf_state(device_t dev) {
+ unsigned port = dev>>8;
+ outb(0x87, port);
+}
+
+static void pnp_exit_conf_state(device_t dev) {
+ unsigned port = dev>>8;
+ outb(0xaa, port);
+}
+
+static void f71805f_enable_serial(device_t dev, unsigned iobase)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
--
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