Author: uwe
Date: 2007-05-09 09:52:14 +0200 (Wed, 09 May 2007)
New Revision: 2641
Added:
trunk/LinuxBIOSv2/src/mainboard/asi/
trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/
trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/Config.lb
trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/Options.lb
trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/auto.c
trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/chip.h
trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/irq_tables.c
trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/mainboard.c
trunk/LinuxBIOSv2/targets/asi/
trunk/LinuxBIOSv2/targets/asi/mb_5blmp/
trunk/LinuxBIOSv2/targets/asi/mb_5blmp/Config.lb
Log:
Add initial support for the ASI/BCom MB-5BLMP mainboard, as used in
the IGEL Winnet III thin client.
It boots a Linux kernel, but there are some problems. The login
prompt is never reached, it simply hangs at some point.
One possible reason is the IRQ table, which needs fixing.
Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>
Added: trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/Config.lb
(rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/Config.lb 2007-05-09
07:52:14 UTC (rev 2641)
@@ -0,0 +1,209 @@
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+ default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
+ default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET
+ 1)
+default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+##
+## Set all of the defaults for an x86 architecture
+##
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+
+if HAVE_PIRQ_TABLE
+ object irq_tables.o
+end
+
+##
+## Romcc output
+##
+# makerule ./failover.E
+# depends "$(MAINBOARD)/failover.c ./romcc"
+# action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I.
$(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+# end
+#
+# makerule ./failover.inc
+# depends "$(MAINBOARD)/failover.c ./romcc"
+# action "./romcc -O --label-prefix=failover -I$(TOP)/src -I.
$(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+# end
+
+makerule ./auto.E
+ depends "$(MAINBOARD)/auto.c ./romcc"
+ action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS)
$(MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc
+ depends "$(MAINBOARD)/auto.c ./romcc"
+ action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS)
$(MAINBOARD)/auto.c -o $@"
+end
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+end
+
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### This is the early phase of linuxBIOS startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+# if USE_FALLBACK_IMAGE
+# ldscript /arch/i386/lib/failover.lds
+# mainboardinit ./failover.inc
+# end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/amd/model_gx1/cpu_setup.inc
+mainboardinit cpu/amd/model_gx1/gx_setup.inc
+mainboardinit ./auto.inc
+
+##
+## Include the secondary Configuration files
+##
+dir /pc80
+config chip.h
+
+chip northbridge/amd/gx1 # Northbridge
+ device pci_domain 0 on
+ device pci 0.0 on end
+ chip southbridge/amd/cs5530 # Southbridge
+ device pci 12.0 on
+ chip superio/nsc/pc87351 # Super I/O
+ device pnp 2e.0 on # PIC
+ io 0x60 = 0x20
+ io 0x62 = 0xa0
+ irq 0x70 = 2
+ end
+ device pnp 2e.1 on # DMA
+ end
+ device pnp 2e.2 on # System Timer
+ io 0x60 = 0x40
+ irq 0x70 = 0
+ end
+ device pnp 2e.3 on # RTC
+ io 0x60 = 0x70
+ irq 0x70 = 8
+ end
+ device pnp 2e.4 on # Keyboard + Mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.5 on # PC Speaker
+ end
+ device pnp 2e.6 on # Math Coprocessor (FPU)
+ io 0x60 = 0xf0
+ irq 0x70 = 13
+ end
+ device pnp 2e.7 on # System board
+ end
+ device pnp 2e.8 on # Motherboard resources
+ end
+ device pnp 2e.9 on # PCI bus
+ end
+ device pnp 2e.c on # Motherboard resources
+ end
+ device pnp 2e.d on # Motherboard resources
+ end
+ device pnp 2e.e on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.f off # FDC
+ end
+ device pnp 2e.10 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.12 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ end
+ device pci 12.1 off end # SMI
+ device pci 12.2 on end # IDE
+ device pci 12.3 off end # Audio
+ device pci 12.4 off end # Video (VGA)
+ end
+ # device pci 12.4 on # VGA (onboard)
+ # chip drivers/pci/onboard
+ # device pci 12.4 on end
+ # register "rom_address" = "0xfffc0000" # 256 KB image
+ # # register "rom_address" = "0xfff80000" # 512 KB image
+ # # register "rom_address" = "0xfff00000" # 1 MB image
+ # end
+ # end
+ device pci 0f.0 off end # Ethernet (Realtek RTL8139B)
+ device pci 13.0 on end # USB
+ end
+ end
+
+ chip cpu/amd/model_gx1 # CPU
+ end
+
+end
+
Added: trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/Options.lb
(rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/Options.lb 2007-05-09
07:52:14 UTC (rev 2641)
@@ -0,0 +1,160 @@
+uses HAVE_PIRQ_TABLE
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses CONFIG_ROM_PAYLOAD
+uses IRQ_SLOT_COUNT
+uses MAINBOARD
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PART_NUMBER
+uses LINUXBIOS_EXTRA_VERSION
+uses ARCH
+uses FALLBACK_SIZE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_PAYLOAD_START
+# uses CONFIG_COMPRESS
+# uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
+# uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses _RAMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_CONSOLE_SERIAL8250
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses CONFIG_UDELAY_TSC
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+# uses CONFIG_CONSOLE_VGA
+# uses CONFIG_PCI_ROM_RUN
+
+
+## ROM_SIZE is the size of boot ROM that this board will use.
+default ROM_SIZE = 256 * 1024
+
+###
+### Build options
+###
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=0
+
+## Delay timer options
+##
+default CONFIG_UDELAY_TSC=1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=5 # TODO?
+
+##
+## Build code to export a CMOS option table
+##
+# default HAVE_OPTION_TABLE=0
+
+###
+### LinuxBIOS layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 64 * 1024
+default FALLBACK_SIZE = 128 * 1024
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 16K heap
+##
+default HEAP_SIZE=0x4000
+
+##
+## Only use the option table in a normal image
+##
+#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+# default USE_OPTION_TABLE = 0
+
+default _RAMBASE = 0x00004000
+
+default CONFIG_ROM_PAYLOAD = 1
+
+##
+## The default compiler
+##
+default CROSS_COMPILE=""
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3
+
+##
+### Select the linuxBIOS loglevel
+##
+## EMERG 1 system is unusable
+## ALERT 2 action must be taken immediately
+## CRIT 3 critical conditions
+## ERR 4 error conditions
+## WARNING 5 warning conditions
+## NOTICE 6 normal but significant condition
+## INFO 7 informational
+## DEBUG 8 debug-level messages
+## SPEW 9 Way too many details
+
+## Request this level of debugging output
+default DEFAULT_CONSOLE_LOGLEVEL=9
+## At a maximum only compile in this level of debugging
+default MAXIMUM_CONSOLE_LOGLEVEL=9
+
+# VGA Console
+# default CONFIG_CONSOLE_VGA=1
+# default CONFIG_PCI_ROM_RUN=1
+
+end
+
Added: trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/auto.c
(rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/auto.c 2007-05-09 07:52:14 UTC
(rev 2641)
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+#include "northbridge/amd/gx1/raminit.c"
+#include "superio/nsc/pc87351/pc87351_early_serial.c"
+#include "cpu/x86/bist.h"
+
+#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
+
+static void main(unsigned long bist)
+{
+ /* Initialize the serial console. */
+ pc87351_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ uart_init();
+ console_init();
+
+ /* Halt if there was a built in self test failure. */
+ report_bist_failure(bist);
+
+ /* Initialize RAM. */
+ sdram_init();
+
+ /* Check whether RAM works. */
+ /* ram_check(0x00000000, 0x4000); */
+}
Added: trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/chip.h
(rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/chip.h 2007-05-09 07:52:14 UTC
(rev 2641)
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_asi_mb_5blmp_ops;
+
+struct mainboard_asi_mb_5blmp_config {
+ int nothing;
+};
Added: trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/irq_tables.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/irq_tables.c
(rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/irq_tables.c 2007-05-09
07:52:14 UTC (rev 2641)
@@ -0,0 +1,39 @@
+/* TODO: This is currently copied from the IEI NOVA-4899R target, but it's
+ * quite surely wrong for this board. It gets me further in the boot process
+ * than using no irq_tables.c file at all, though!
+ */
+
+/* TODO: Add license header. */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32+16*5, /* there can be total 5 devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
+ 0xe00, /* IRQs devoted exclusively to PCI usage */
+ 0x1078, /* Vendor */
+ 0x0002, /* Device */
+ 0, /* Crap (miniport) */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x2d, /* u8 checksum , this hase to set to some value that
would give 0 after the sum of all bytes for this structure (including checksum)
*/
+ {
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link,
bitmap}, {link, bitmap}, slot, rfu */
+ // USB
+ {0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00,
0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
+ // eth0
+ {0x00,(0x0a<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04,
0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},//0x3, 0x0},
+ // eth1
+ {0x00,(0x0b<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x02,
0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},//0x2, 0x0},
+ // eth2
+ {0x00,(0x0c<<3)|0x0, {{0x04, 0xdeb8}, {0x02, 0xdeb8}, {0x03,
0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},//0x1, 0x0},
+ // PCI slot
+ {0x00,(0x0f<<3)|0x0, {{0x04, 0xdeb8}, {0x03, 0xdeb8}, {0x02,
0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
+ }
+};
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
+}
Added: trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/mainboard.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/mainboard.c
(rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/mainboard.c 2007-05-09
07:52:14 UTC (rev 2641)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_asi_mb_5blmp_ops = {
+ CHIP_NAME("ASI/BCom MB-5BLMP Mainboard")
+};
+
Added: trunk/LinuxBIOSv2/targets/asi/mb_5blmp/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/targets/asi/mb_5blmp/Config.lb
(rev 0)
+++ trunk/LinuxBIOSv2/targets/asi/mb_5blmp/Config.lb 2007-05-09 07:52:14 UTC
(rev 2641)
@@ -0,0 +1,43 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2007 Uwe Hermann <[EMAIL PROTECTED]>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+target mb_5blmp
+mainboard asi/mb_5blmp
+
+option ROM_SIZE = (256 * 1024)
+# option ROM_SIZE = (256 * 1024) - (32 * 1024)
+# option FALLBACK_SIZE = (256 * 1024) - (32 * 1024)
+
+romimage "normal"
+ option USE_FALLBACK_IMAGE = 0
+ option ROM_IMAGE_SIZE = 64 * 1024
+ option LINUXBIOS_EXTRA_VERSION = ".0Normal"
+ payload /tmp/filo.elf
+end
+
+romimage "fallback"
+ option USE_FALLBACK_IMAGE = 1
+ option ROM_IMAGE_SIZE = 64 * 1024
+ option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
+ payload /tmp/filo.elf
+end
+
+buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+# buildrom ./linuxbios.rom ROM_SIZE "fallback"
--
linuxbios mailing list
linuxbios@linuxbios.org
http://www.linuxbios.org/mailman/listinfo/linuxbios
