Uwe Hermann wrote:
> On Tue, May 15, 2007 at 04:03:19PM -0400, Corey Osgood wrote:
>>> Just to prevent unnecessary duplicated work: please don't write
>>> SPD-related functions for 440BX. I'm about to finish a patch which moves
>>> all generic SPD-related functions into src/sdram/spd.c where all
>>> chipsets can use them.
>>>
>>> The SPD-only stuff should be chipset-independent, only the
>>> chipset-specific stuff should be handled in the respective raminit.c.
>> That figures. Just finished a ton of SPD stuff for the 440bx last night.
>
> Hm, sorry... I only started on this patch today, I hope this didn't
> cause too much trouble...
>
> I'll post a draft soon, so that people can see which functions are
> affected. This needs an abuild-run and tests on a bunch of different
> hardware targets to make sure nothing breaks...
Well, if you want to compare notes at all, I've attached my raminit.c
(the file, not a patch). If you could, please maintain the MODEL_440ZX
stuff, as that's necessary for 440zx support. MODEL_440ZX will be
defined in the mainboard auto.c, once this is all up and running, and
those ifdef's are the ONLY differences between the two northbridges.
However, there's no way to detect the difference at runtime that I can
find, so a define is the only real way.
>> Any luck on getting cache-as-ram going? I'm running out of registers
>> with my code, perhaps yours is more register-friendly.
>
> I have a version which _compiles_, but I haven't tested on real hardware
> whether it actually works. Will do so soon, though.
Well, good luck! I've got the rest of the day free, so I hope to hear
from you soon.
-Corey
/*
* This file is part of the LinuxBIOS project.
*
* Copyright (C) 2007 Uwe Hermann <[EMAIL PROTECTED]>
* Copyright (C) 2007 Corey Osgood <[EMAIL PROTECTED]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <spd.h>
#include <sdram_mode.h>
#include <delay.h>
#include "i440bx.h"
/*-----------------------------------------------------------------------------
Macros and definitions.
-----------------------------------------------------------------------------*/
/* Uncomment this to enable debugging output. */
#define DEBUG_RAM_SETUP 1
/* Debugging macros. */
#if defined(DEBUG_RAM_SETUP)
#define PRINT_DEBUG(x) print_debug(x)
#define PRINT_DEBUG_HEX8(x) print_debug_hex8(x)
#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
#define PRINT_DEBUG_HEX32(x) print_debug_hex32(x)
#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
#else
#define PRINT_DEBUG(x)
#define PRINT_DEBUG_HEX8(x)
#define PRINT_DEBUG_HEX16(x)
#define PRINT_DEBUG_HEX32(x)
#define DUMPNORTH()
#endif
/* SDRAMC[7:5] - SDRAM Mode Select (SMS). */
#define RAM_COMMAND_NORMAL 0x0
#define RAM_COMMAND_NOP 0x1
#define RAM_COMMAND_PRECHARGE 0x2
#define RAM_COMMAND_MRS 0x3
#define RAM_COMMAND_CBR 0x4
/* Map the JEDEC SPD refresh rates (array index) to 440BX refresh rates as
* defined in DRAMC[2:0].
*
* [0] == Normal 15.625 us -> 15.6 us
* [1] == Reduced(.25X) 3.9 us -> 7.8 ns
* [2] == Reduced(.5X) 7.8 us -> 7.8 us
* [3] == Extended(2x) 31.3 us -> 31.2 us
* [4] == Extended(4x) 62.5 us -> 62.4 us
* [5] == Extended(8x) 125 us -> 124.8 us
*/
static const uint32_t refresh_rate_map[] = {
1, 5, 5, 2, 3, 4
};
/* Table format: register, bitmask, value. */
static const long register_values[] = {
/* DRAMC - DRAM Control Register
* 0x57
*
* [7:6] Reserved
* [5:5] Module Mode Configuration (MMCONFIG)
* Set by external strapping options
* SDRAMPWR MMCONFIG CKE Operation
* 0 0 3 DIMM, CKE[5:0] driven, self-refresh entry
* staggered. SDRAM dynamic power down available.
* X 1 3 DIMM, CKE0 only, self-refresh entry not
* staggered. SDRAM dynamic power down unavailable.
* 1 0 4 DIMM, GCKE only, self-refresh entry staggered.
* SDRAM dynamic power down unavailable.
* [4:3] DRAM Type (DT)
* 00 = EDO
* 01 = SDRAM
* 10 = Registered SDRAM
* 11 = Reserved
* Note: EDO, SDRAM and Registered SDRAM cannot be mixed.
* [2:0] DRAM Refresh Rate (DRR)
* 000 = Refresh disabled
* 001 = 15.6 us
* 010 = 31.2 us
* 011 = 62.4 us
* 100 = 124.8 us
* 101 = 249.6 us
* 110 = Reserved
* 111 = Reserved
*/
/* Choose SDRAM (not registered), and disable refresh for now. */
DRAMC, 0x00, 0x8,
/*
* PAM[6:0] - Programmable Attribute Map Registers
*
* 0x59 [3:0] Reserved
* 0x59 [5:4] 0xF0000 - 0xFFFFF BIOS area
* 0x5a [1:0] 0xC0000 - 0xC3FFF ISA add-on BIOS
* 0x5a [5:4] 0xC4000 - 0xC7FFF ISA add-on BIOS
* 0x5b [1:0] 0xC8000 - 0xCBFFF ISA add-on BIOS
* 0x5b [5:4] 0xCC000 - 0xCFFFF ISA add-on BIOS
* 0x5c [1:0] 0xD0000 - 0xD3FFF ISA add-on BIOS
* 0x5c [5:4] 0xD4000 - 0xD7FFF ISA add-on BIOS
* 0x5d [1:0] 0xD8000 - 0xDBFFF ISA add-on BIOS
* 0x5d [5:4] 0xDC000 - 0xDFFFF ISA add-on BIOS
* 0x5e [1:0] 0xE0000 - 0xE3FFF BIOS entension
* 0x5e [5:4] 0xE4000 - 0xE7FFF BIOS entension
* 0x5f [1:0] 0xE8000 - 0xEBFFF BIOS entension
* 0x5f [5:4] 0xEC000 - 0xEFFFF BIOS entension
*
* Bit assignment:
* 00 = DRAM Disabled (all access goes to memory mapped I/O space)
* 01 = Read Only (Reads to DRAM, writes to memory mapped I/O space)
* 10 = Write Only (Writes to DRAM, reads to memory mapped I/O space)
* 11 = Read/Write (all access goes to DRAM)
*/
// TODO
PAM0, 0x00000000, 0x00,
PAM1, 0x00000000, 0x00,
PAM2, 0x00000000, 0x00,
PAM3, 0x00000000, 0x00,
PAM4, 0x00000000, 0x00,
PAM5, 0x00000000, 0x00,
PAM6, 0x00000000, 0x00,
/* FDHC - Fixed DRAM Hole Control Register
* 0x68
*
* Controls two fixed DRAM holes: 512 KB - 640 KB and 15 MB - 16 MB.
*
* [7:6] Hole Enable (HEN)
* 00 = None
* 01 = 512 KB - 640 KB (128 KB)
* 10 = 15 MB - 16 MB (1 MB)
* 11 = Reserved
* [5:0] Reserved
*/
/* No memory holes. */
FDHC, 0x00, 0x00,
/* RPS - SDRAM Row Page Size Register
* 0x74 - 0x75
*
* Sets the row page size for SDRAM. For EDO memory, the page
* size is fixed at 2 KB.
*
* [15:0] Page Size (PS)
* TODO
*/
// TODO
//RPS, 0x0000, 0x0000,
/* SDRAMC - SDRAM Control Register
* 0x76 - 0x77
*
* [15:10] Reserved
* [09:08] Idle/Pipeline DRAM Leadoff Timing (IPDLT)
* 00 = Illegal
* 01 = Add a clock delay to the lead-off clock count
* 10 = Illegal
* 11 = Illegal
* [07:05] SDRAM Mode Select (SMS)
* 000 = Normal SDRAM Operation (default)
* 001 = NOP Command Enable
* 010 = All Banks Precharge Enable
* 011 = Mode Register Set Enable
* 100 = CBR Enable
* 101 = Reserved
* 110 = Reserved
* 111 = Reserved
* [04:04] SDRAMPWR
* 0 = 3 DIMM configuration
* 1 = 4 DIMM configuration
* [03:03] Leadoff Command Timing (LCT)
* 0 = 4 CS# Clock
* 1 = 3 CS# Clock
* [02:02] CAS# Latency (CL)
* 0 = 3 DCLK CAS# latency
* 1 = 2 DCLK CAS# latency
* [01:01] SDRAM RAS# to CAS# Delay (SRCD)
* 0 = 3 clocks between a row activate and a read or write cmd.
* 1 = 2 clocks between a row activate and a read or write cmd.
* [00:00] SDRAM RAS# Precharge (SRP)
* 0 = 3 clocks of RAS# precharge
* 1 = 2 clocks of RAS# precharge
*/
SDRAMC, 0x0000, 0x0000,
/* PGPOL - Paging Policy Register
* 0x78 - 0x79
*
* [15:08] Banks per Row (BPR)
* TODO
* 0 = 2 banks
* 1 = 4 banks
* [07:05] Reserved
* [04:04] Intel Reserved
* [03:00] DRAM Idle Timer (DIT)
* 0000 = 0 clocks
* 0001 = 2 clocks
* 0010 = 4 clocks
* 0011 = 8 clocks
* 0100 = 10 clocks
* 0101 = 12 clocks
* 0110 = 16 clocks
* 0111 = 32 clocks
* 1xxx = Infinite (pages are not closed for idle condition)
*/
// TODO
PGPOL, 0x0000, 0xff00,
/* PMCR - Power Management Control Register
* 0x7a
*
* [07:07] Power Down SDRAM Enable (PDSE)
* 1 = Enable
* 0 = Disable
* [06:06] ACPI Control Register Enable (SCRE)
* 1 = Enable
* 0 = Disable (default)
* [05:05] Suspend Refresh Type (SRT)
* 1 = Self refresh mode
* 0 = CBR fresh mode
* [04:04] Normal Refresh Enable (NREF_EN)
* 1 = Enable
* 0 = Disable
* [03:03] Quick Start Mode (QSTART)
* 1 = Quick start mode for the processor is enabled
* [02:02] Gated Clock Enable (GCLKEN)
* 1 = Enable
* 0 = Disable
* [01:01] AGP Disable (AGP_DIS)
* 1 = Disable
* 0 = Enable
* [00:00] CPU reset without PCIRST enable (CRst_En)
* 1 = Enable
* 0 = Disable
*/
/* Enable normal refresh and the gated clock. */
// TODO: Only do this later?
// PMCR, 0x00, 0x14,
// PMCR, 0x00, 0x10,
PMCR, 0x00, 0x00,
};
/*-----------------------------------------------------------------------------
SDRAM configuration functions.
-----------------------------------------------------------------------------*/
/**
* Send the specified RAM command to all DIMMs.
*
* @param Memory controller
* @param TODO
* @param TODO
*/
static void do_ram_command(const struct mem_controller *ctrl,
uint32_t command, uint32_t addr_offset)
{
int i;
uint16_t reg;
/* TODO: Support for multiple DIMMs. */
/* Configure the RAM command. */
reg = pci_read_config16(ctrl->d0, SDRAMC);
reg &= 0xff1f; /* Clear bits 7-5. */
reg |= (uint16_t) (command << 5);
pci_write_config16(ctrl->d0, SDRAMC, reg);
/* RAM_COMMAND_NORMAL affects only the memory controller and
doesn't need to be "sent" to the DIMMs. */
/* if (command == RAM_COMMAND_NORMAL) return; */
PRINT_DEBUG(" Sending RAM command 0x");
PRINT_DEBUG_HEX16(reg);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(0 + addr_offset); // FIXME
PRINT_DEBUG("\r\n");
/* Read from (DIMM start address + addr_offset). */
read32(0 + addr_offset); // FIXME
}
/*-----------------------------------------------------------------------------
DIMM-independant configuration functions.
-----------------------------------------------------------------------------*/
/**
* TODO.
*
* @param Memory controller
*/
static void spd_enable_refresh(const struct mem_controller *ctrl)
{
int i, value;
uint8_t reg;
reg = pci_read_config8(ctrl->d0, DRAMC);
for (i = 0; i < DIMM_SOCKETS; i++) {
value = smbus_read_byte(ctrl->channel0[i], SPD_REFRESH);
if (value < 0)
continue;
reg = (reg & 0xf8) | refresh_rate_map[(value & 0x7f)];
PRINT_DEBUG(" Enabling refresh (DRAMC = 0x");
PRINT_DEBUG_HEX8(reg);
PRINT_DEBUG(") for DIMM ");
PRINT_DEBUG_HEX8(i);
PRINT_DEBUG("\r\n");
}
pci_write_config8(ctrl->d0, DRAMC, reg);
}
static void spd_set_nbxcfg(const struct mem_controller *ctrl)
{
uint32_t nbxcfg = 0x0;
int i, spd_data;
/* NBXCFG - NBX Configuration Register
* 0x50
*
* [31:24] SDRAM Row Without ECC
* 0 = ECC components are populated in this row
* 1 = ECC components are not populated in this row */
/* Note: there's no way to tell 440zx from bx via hardware */
/* 440ZX doesn't do ECC, and needs bits 31-24 set to 0, so skip this */
#ifndef MODEL_440ZX
for(i = 0; i < 4; i++)
{
/* Check if this dimm supports ECC */
spd_data = smbus_read_byte(ctrl->channel0[i], 11);
/* If it does *not*, or there's no dimm present, set bits for both
sides to disable ECC, otherwise leave them enabled */
if(spd_data != 2)
{
/* This may need to be fixed for single-sided ECC SDRAM */
nbxcfg |= 3 << (31 - (i * 2));
}
}
#endif
/* [23:19] Reserved
* [18:18] Host Bus Fast Data Ready Enable (HBFDRE)
* Assertion of DRAM data on host bus occurs...
* 0 = ...one clock after sampling snoop results (default)
* 1 = ...on the same clock the snoop result is being sampled
* (this mode is faster by one clock cycle)
* [17:17] ECC - EDO static Drive mode
* 0 = Normal mode (default)
* 1 = ECC signals are always driven
* [16:16] IDSEL_REDIRECT
* 0 = IDSEL1 is allocated to this bridge (default)
* 1 = IDSEL7 is allocated to this bridge
* [15:15] WSC# Handshake Disable
* 1 = Uni-processor mode
* 0 = Dual-processor mode with external IOAPIC (default) */
/* TODO: runtime detection? */
#if CONFIG_SMP == 0
nbxcfg |= 1 << 15;
#endif
/* [14:14] Intel Reserved
* [13:12] Host/DRAM Frequency
* 00 = 100 MHz
* 01 = Reserved
* 10 = 66 MHz
* 11 = Reserved */
/* Set the DRAM frequency to the lowest of all dimms */
/* TODO: do this with the previous loop */
for(i = 0; i < 4; i++)
{
spd_data = smbus_read_byte(ctrl->channel0[i], 126);
/* If we find any 66MHz dimms, set the dimm speed to 66MHz and break */
/* Note: This depends on the dimm following the Intel SPD standard */
if(spd_data == 0x66)
{
nbxcfg |= 1 << 13;
i = 6; //just to make sure
break;
}
}
/* [11:11] AGP to PCI Access Enable
* 1 = Enable
* 0 = Disable
* [10:10] PCI Agent to Aperture Access Disable
* 1 = Disable
* 0 = Enable (default)
* [09:09] Aperture Access Global Enable
* 1 = Enable
* 0 = Disable
TODO: We need to define an agp aperture and enable it, possibly later in init
* [08:07] DRAM Data Integrity Mode (DDIM)
* 00 = Non-ECC
* 01 = EC-only
* 10 = ECC Mode
* 11 = ECC Mode with hardware scrubbing enabled
TODO: ECC needs to be enabled here. I have no ecc memory to test with,
so I'm leaving it to somone else
* [06:06] ECC Diagnostic Mode Enable (EDME)
* 1 = Enable
* 0 = Normal operation mode (default)
* [05:05] MDA Present (MDAP)
* Works in conjunction with the VGA_EN bit.
* VGA_EN MDAP
* 0 x All VGA cycles are sent to PCI
* 1 0 All VGA cycles are sent to AGP
* 1 1 All VGA cycles are sent to AGP, except for
* cycles in the MDA range.
* [04:04] Reserved
* [03:03] USWC Write Post During I/O Bridge Access Enable (UWPIO)
* 1 = Enable
* 0 = Disable
* [02:02] In-Order Queue Depth (IOQD)
* 1 = In-order queue = maximum
* 0 = A7# is sampled asserted (i.e., 0)
* [01:00] Reserved
*/
nbxcfg |= 0xc; //sets bits 3 and 2 to 1
PRINT_DEBUG("Value of NBXCFG calculated to 0x");
PRINT_DEBUG_HEX32(nbxcfg);
PRINT_DEBUG("/r/n");
pci_write_config8(ctrl->d0, NBXCFG, nbxcfg);
}
static void spd_set_dram_size(const struct mem_controller *ctrl)
{
/* DRB[0:7] - DRAM Row Boundary Registers
* 0x60 - 0x67
*
* An array of 8 byte registers, which hold the ending memory address
* assigned to each pair of DIMMs, in 8MB granularity.
*
* 0x60 DRB0 = Total memory in row0 (in 8 MB)
* 0x61 DRB1 = Total memory in row0+1 (in 8 MB)
* 0x62 DRB2 = Total memory in row0+1+2 (in 8 MB)
* 0x63 DRB3 = Total memory in row0+1+2+3 (in 8 MB)
* 0x64 DRB4 = Total memory in row0+1+2+3+4 (in 8 MB)
* 0x65 DRB5 = Total memory in row0+1+2+3+4+5 (in 8 MB)
* 0x66 DRB6 = Total memory in row0+1+2+3+4+5+6 (in 8 MB)
* 0x67 DRB7 = Total memory in row0+1+2+3+4+5+6+7 (in 8 MB)
*/
int i, dimm_size, rows, row_size, running_total;
/* We're going to set RPS while we're in here too */
uint16_t rps = 0x0000;
running_total = 0;
/* Count to 8 since there are 8 possible rows, but count by 2 to check by dimm */
/* Should 8 be replaced with DIMM_SOCKETS * 2? */
for(i = 0; i < 8; i = i + 2)
{
/* First check if this row is populated with SDR SDRAM */
if(smbus_read_byte(ctrl->channel0[i/2], 2) == 0x04)
{
rows = smbus_read_byte(ctrl->channel0[i/2], 5);
/* FIXME: We're assuming symetrical dimms! */
row_size = smbus_read_byte(ctrl->channel0[i/2], 31);
/* Now figure out what the size of the dimm is */
/* row_size (spd byte 31) is in incriments of 4MB */
dimm_size = rows * row_size * 4;
print_debug("Found 0x");
print_debug_hex8(dimm_size);
print_debug("MB DIMM in slot ");
print_debug_hex8(i/2);
print_debug("\r\n");
/* Convert dimms_size to be in 8MB chunks */
dimm_size = dimm_size >> 3;
/* Here we're going to reuse rows to figure out if we're
dealing with a dual-sided dimm */
/* Note: this relies on dimms following Intel SPD standard */
rows = smbus_read_byte(ctrl->channel0[i/2], 127) >> 4;
if(rows & 0xf == 0xf)//then we have a dual sided dimm
{
print_debug("DIMM is dual-sided\r\n");
running_total += (dimm_size/2);
pci_write_config8(ctrl->d0, DRB0 + i, running_total);
running_total += (dimm_size/2);
pci_write_config8(ctrl->d0, DRB0 + i + 1, running_total);
rps &= 5 << i;
} else { //we have a single sided dimm
running_total += dimm_size;
pci_write_config8(ctrl->d0, DRB0 + i, running_total);
rps &= 1 << i;
}
}
else
{
print_debug("No DIMM detected in slot ");
print_debug_hex8(i/2);
print_debug("\r\n");
}
}
PRINT_DEBUG("Row Page Size Register (RPS) calculated to 0x");
PRINT_DEBUG_HEX16(rps);
PRINT_DEBUG("\r\n");
pci_write_config16(ctrl->d0, RPS, rps);
}
static void set_spd_timing(const struct mem_controller *ctrl)
{
int i, cas, ras, rcd, memclk;
uint16_t sdramc = 0x0000;
cas = 1;
ras = 0;//set these back to 1 once the code is fixed
rcd = 0;
/* Read the SDRAM speed from the northbridge, where we set it earlier */
if(pci_read_config8(ctrl->d0, NBXCFG) >> 13 & 1 == 1)
{
/* These need to be changed to be the clock time in ns */
memclk = 66;
} else {
memclk = 100;
}
/* Start by assuming CAS=2, RCD=2, and RAS=2. If we find ANY dimms that
don't support those timings, set them higher */
/* TODO: RAS and RCD need math to calculate what the target value is */
for(i = 0; i < 4; i++)
{
/* Lots of nested loops, probably not the best way */
if(smbus_read_byte(ctrl->channel0[i], 2) == 0x4)
{
if(smbus_read_byte(ctrl->channel0[i], 18) & 2 != 2) cas = 0;
}
}
sdramc = (cas << 2) + (rcd << 1) + ras;
pci_write_config16(ctrl->d0, SDRAMC, sdramc);
}
/*-----------------------------------------------------------------------------
Public interface.
-----------------------------------------------------------------------------*/
/**
* TODO.
*
* @param Memory controller
*/
static void sdram_set_registers(const struct mem_controller *ctrl)
{
int i, max;
uint32_t reg;
PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n");
DUMPNORTH();
max = sizeof(register_values) / sizeof(register_values[0]);
/* Set registers as specified in the register_values array. */
for (i = 0; i < max; i += 3) {
reg = pci_read_config32(ctrl->d0, register_values[i]);
reg &= register_values[i + 1];
reg |= register_values[i + 2] & ~(register_values[i + 1]);
pci_write_config32(ctrl->d0, register_values[i], reg);
PRINT_DEBUG(" Set register 0x");
PRINT_DEBUG_HEX32(register_values[i]);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(reg);
PRINT_DEBUG("\r\n");
}
}
/**
* TODO.
*
* @param Memory controller
*/
static void sdram_set_spd_registers(const struct mem_controller *ctrl)
{
spd_set_nbxcfg(ctrl);
spd_set_dram_size(ctrl);
/* TODO: Set DRAMC. Don't enable refresh for now. */
/* Leave this be for now, it only needs to be changed if someone wants to
use EDO memory with it */
pci_write_config8(ctrl->d0, DRAMC, 0x08);
set_spd_timing(ctrl);
/* TODO: Set PGPOL. */
pci_write_config16(ctrl->d0, PGPOL, 0x0107);
/* TODO: Set PMCR? */
// pci_write_config8(ctrl->d0, PMCR, 0x14);
// pci_write_config8(ctrl->d0, PMCR, 0x10);
/* TODO? */
// pci_write_config8(ctrl->d0, MLT, 0x40);
// pci_write_config8(ctrl->d0, DRAMT, 0x03);
// pci_write_config8(ctrl->d0, MBSC, 0x03);
// pci_write_config8(ctrl->d0, SCRR, 0x38);
}
/**
* Enable SDRAM.
*
* @param Number of controllers
* @param Memory controller
*/
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
{
int i;
/* TODO: Use a delay here? Needed? */
mdelay(200);
/* TODO: How long should the delays be? Fix later. */
/* 1. Apply NOP. */
PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
do_ram_command(ctrl, RAM_COMMAND_NOP, 0);
mdelay(10);
/* 2. Precharge all. Wait tRP. */
PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0);
mdelay(10);
/* 3. Perform 8 refresh cycles. Wait tRC each time. */
PRINT_DEBUG("RAM Enable 3: CBR\r\n");
do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
for (i = 0; i < 8; i++) {
read32(0);
mdelay(10);
}
/* 4. Mode register set. Wait two memory cycles. */
PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
if(pci_read_config8(ctrl->d0, SDRAMC) >> 2 & 1 == 1)
{
/* If we are running at CL2 */
do_ram_command(ctrl, RAM_COMMAND_MRS, 0x150);
} else {
/* We're doing CL3 */
do_ram_command(ctrl, RAM_COMMAND_MRS, 0x1d0);
}
mdelay(10);
mdelay(10);
/* 5. Normal operation. */
PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0);
mdelay(10);
/* 6. Finally enable refresh. */
PRINT_DEBUG("RAM Enable 6: Enable refresh\r\n");
// pci_write_config8(ctrl->d0, PMCR, 0x10);
spd_enable_refresh(ctrl);
mdelay(10);
PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
DUMPNORTH();
}
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