I'm usually totally _against_ dropping any targets, but these seem totally non-working, and so incomplete that there's barely _any_ code which is specific to them. Almost all of the code is generic framework, copy+pasted code from other targets.
The only "real" content I can see right now is info from irq_tables.c. Please correct me if I'm wrong, but this code has never worked at all, and doesn't contain anything useful which would warrant keeping it, correct? (after dropping it, the code is still available in the svn history, so even _if_ we'd need any of it later -- which I doubt -- it'll be there) Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
Drop the (non-working, almost non-existant) support for
- the Transmeta TM5800 northbridge
- the Densitron DPX114 mainboard (the only one using the TM5800)
Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Index: src/mainboard/densitron/dpx114/Config.lb
===================================================================
--- src/mainboard/densitron/dpx114/Config.lb (Revision 2680)
+++ src/mainboard/densitron/dpx114/Config.lb (Arbeitskopie)
@@ -1,147 +0,0 @@
-##
-## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The linuxBIOS bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of linuxBIOS will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if HAVE_PIRQ_TABLE object irq_tables.o end
-#object reset.o
-
-##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ./romcc"
- action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ./romcc"
- action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
- action "./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
- action "./romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit linuxBIOS entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where linuxBIOS is entered)
-##
-if USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/reset16.inc
- ldscript /cpu/x86/16bit/reset16.lds
-else
- mainboardinit cpu/x86/32bit/reset32.inc
- ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of linuxBIOS startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-##
-## Include the secondary Configuration files
-##
-dir /pc80
-config chip.h
-
-chip northbridge/via/vt8601
- device pci_domain 0 on
- chip southbridge/via/vt8231
- register "enable_usb" = "0"
- register "enable_native_ide" = "0"
- register "enable_com_ports" = "1"
- register "enable_keyboard" = "0"
- register "enable_nvram" = "1"
-# device pci 0:11.0 on end
-# device pci 0:11.1 on end
-# device pci 0:11.2 on end
-# device pci 0:11.3 on end
-# device pci 0:11.4 on end
-# device pci 0:11.5 on end
-# device pci 0:11.6 on end
-# device pci 0:12.0 on end
- end
- end
- chip cpu/via/model_centaur
- end
-end
Index: src/mainboard/densitron/dpx114/reset.c
===================================================================
--- src/mainboard/densitron/dpx114/reset.c (Revision 2680)
+++ src/mainboard/densitron/dpx114/reset.c (Arbeitskopie)
@@ -1,43 +0,0 @@
-#if 0
-//#include "arch/romcc_io.h"
-#include <arch/io.h>
-
-typedef unsigned device_t;
-
-#define PCI_DEV(BUS, DEV, FN) ( \
- (((BUS) & 0xFF) << 16) | \
- (((DEV) & 0x1f) << 11) | \
- (((FN) & 0x7) << 8))
-
-static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
-{
- unsigned addr;
- addr = dev | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- outb(value, 0xCFC + (addr & 3));
-}
-
-static void pci_write_config32(device_t dev, unsigned where, unsigned value)
-{
- unsigned addr;
- addr = dev | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- outl(value, 0xCFC);
-}
-
-static unsigned pci_read_config32(device_t dev, unsigned where)
-{
- unsigned addr;
- addr = dev | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- return inl(0xCFC);
-}
-
-#include "../../../northbridge/amd/amdk8/reset_test.c"
-
-void hard_reset(void)
-{
- set_bios_reset();
- pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
-}
-#endif
Index: src/mainboard/densitron/dpx114/irq_tables.c
===================================================================
--- src/mainboard/densitron/dpx114/irq_tables.c (Revision 2680)
+++ src/mainboard/densitron/dpx114/irq_tables.c (Arbeitskopie)
@@ -1,34 +0,0 @@
-/* This file was generated by getpir.c, do not modify!
- (but if you do, please run checkpir on it to verify)
- * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
- *
- * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
-*/
-
-#include <arch/pirq_routing.h>
-
-const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*5, /* there can be total 5 devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x00<<3)|0x0, /* Where the interrupt router lies (dev) */
- 0x1ea0, /* IRQs devoted exclusively to PCI usage */
- 0, /* Vendor */
- 0, /* Device */
- 0, /* Crap (miniport) */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x15, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
- {
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x09<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x1, 0x0},
- {0x00,(0x0a<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0},
- {0x00,(0x0b<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0},
- {0x00,(0x0f<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
- {0x00,(0x02<<3)|0x0, {{0x59, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
- }
-};
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr);
-}
Index: src/mainboard/densitron/dpx114/Options.lb
===================================================================
--- src/mainboard/densitron/dpx114/Options.lb (Revision 2680)
+++ src/mainboard/densitron/dpx114/Options.lb (Arbeitskopie)
@@ -1,109 +0,0 @@
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses OBJCOPY
-uses CONFIG_UDELAY_IO
-
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default HAVE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from linuxBIOS
-##
-default HAVE_HARD_RESET=1
-
-##
-## use io based udelay function
-##
-default CONFIG_UDELAY_IO=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=5
-
-##
-## Build code to export a CMOS option table
-##
-default HAVE_OPTION_TABLE=1
-
-###
-### LinuxBIOS layout values
-###
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-default ROM_IMAGE_SIZE = 65536
-default FALLBACK_SIZE = 131072
-
-##
-## Use a small 8K stack
-##
-default STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
-
-default _RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD = 1
-
-##
-## The default compiler
-##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-end
Index: src/mainboard/densitron/dpx114/debug.c
===================================================================
--- src/mainboard/densitron/dpx114/debug.c (Revision 2680)
+++ src/mainboard/densitron/dpx114/debug.c (Arbeitskopie)
@@ -1,128 +0,0 @@
-
-static void print_debug_pci_dev(unsigned dev)
-{
- print_debug("PCI: ");
- print_debug_hex8((dev >> 16) & 0xff);
- print_debug_char(':');
- print_debug_hex8((dev >> 11) & 0x1f);
- print_debug_char('.');
- print_debug_hex8((dev >> 8) & 7);
-}
-
-static void print_pci_devices(void)
-{
- device_t dev;
- for(dev = PCI_DEV(0, 0, 0);
- dev <= PCI_DEV(0, 0x1f, 0x7);
- dev += PCI_DEV(0,0,1)) {
- uint32_t id;
- id = pci_read_config32(dev, PCI_VENDOR_ID);
- if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0x0000)) {
- continue;
- }
- print_debug_pci_dev(dev);
- print_debug("\r\n");
- }
-}
-
-static void dump_pci_device(unsigned dev)
-{
- int i;
- print_debug_pci_dev(dev);
- print_debug("\r\n");
-
- for(i = 0; i <= 255; i++) {
- unsigned char val;
- if ((i & 0x0f) == 0) {
- print_debug_hex8(i);
- print_debug_char(':');
- }
- val = pci_read_config8(dev, i);
- print_debug_char(' ');
- print_debug_hex8(val);
- if ((i & 0x0f) == 0x0f) {
- print_debug("\r\n");
- }
- }
-}
-
-static void dump_pci_devices(void)
-{
- device_t dev;
- for(dev = PCI_DEV(0, 0, 0);
- dev <= PCI_DEV(0, 0x1f, 0x7);
- dev += PCI_DEV(0,0,1)) {
- uint32_t id;
- id = pci_read_config32(dev, PCI_VENDOR_ID);
- if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0x0000)) {
- continue;
- }
- dump_pci_device(dev);
- }
-}
-#if 0
-static void dump_spd_registers(const struct mem_controller *ctrl)
-{
- int i;
- print_debug("\r\n");
- for(i = 0; i < 4; i++) {
- unsigned device;
- device = ctrl->channel0[i];
- if (device) {
- int j;
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".0: ");
- print_debug_hex8(device);
- for(j = 0; j < 256; j++) {
- int status;
- unsigned char byte;
- if ((j & 0xf) == 0) {
- print_debug("\r\n");
- print_debug_hex8(j);
- print_debug(": ");
- }
- status = smbus_read_byte(device, j);
- if (status < 0) {
- print_debug("bad device\r\n");
- break;
- }
- byte = status & 0xff;
- print_debug_hex8(byte);
- print_debug_char(' ');
- }
- print_debug("\r\n");
- }
- device = ctrl->channel1[i];
- if (device) {
- int j;
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".1: ");
- print_debug_hex8(device);
- for(j = 0; j < 256; j++) {
- int status;
- unsigned char byte;
- if ((j & 0xf) == 0) {
- print_debug("\r\n");
- print_debug_hex8(j);
- print_debug(": ");
- }
- status = smbus_read_byte(device, j);
- if (status < 0) {
- print_debug("bad device\r\n");
- break;
- }
- byte = status & 0xff;
- print_debug_hex8(byte);
- print_debug_char(' ');
- }
- print_debug("\r\n");
- }
- }
-}
-#endif
Index: src/mainboard/densitron/dpx114/failover.c
===================================================================
--- src/mainboard/densitron/dpx114/failover.c (Revision 2680)
+++ src/mainboard/densitron/dpx114/failover.c (Arbeitskopie)
@@ -1,32 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include "arch/romcc_io.h"
-#include "pc80/mc146818rtc_early.c"
-
-static unsigned long main(unsigned long bist)
-{
- /* This is the primary cpu how should I boot? */
- if (do_normal_boot()) {
- goto normal_image;
- }
- else {
- goto fallback_image;
- }
- normal_image:
- asm volatile ("jmp __normal_image"
- : /* outputs */
- : "a" (bist) /* inputs */
- : /* clobbers */
- );
- cpu_reset:
- asm volatile ("jmp __cpu_reset"
- : /* outputs */
- : "a"(bist) /* inputs */
- : /* clobbers */
- );
- fallback_image:
- return bist;
-}
Index: src/mainboard/densitron/dpx114/auto.c
===================================================================
--- src/mainboard/densitron/dpx114/auto.c (Revision 2680)
+++ src/mainboard/densitron/dpx114/auto.c (Arbeitskopie)
@@ -1,124 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#if 0
-#include <cpu/x86/lapic.h>
-#endif
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "northbridge/via/vt8601/raminit.h"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-/*
- */
-void udelay(int usecs)
-{
- int i;
- for(i = 0; i < usecs; i++)
- outb(i&0xff, 0x80);
-}
-
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "debug.c"
-
-#include "southbridge/via/vt8231/vt8231_early_smbus.c"
-
-
-#include "southbridge/via/vt8231/vt8231_early_serial.c"
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/via/vt8601/raminit.c"
-
-
-static void enable_mainboard_devices(void)
-{
- device_t dev;
- /* dev 0 for southbridge */
-
- dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
-
- if (dev == PCI_DEV_INVALID) {
- die("Southbridge not found!!!\n");
- }
- pci_write_config8(dev, 0x50, 7);
- pci_write_config8(dev, 0x51, 0xff);
-#if 0
- // This early setup switches IDE into compatibility mode before PCI gets
- // // a chance to assign I/Os
- // movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
- // // movb $0x09, %dl
- // movb $0x00, %dl
- // PCI_WRITE_CONFIG_BYTE
- //
-#endif
- /* we do this here as in V2, we can not yet do raw operations
- * to pci!
- */
- dev += 0x100; /* ICKY */
-
- pci_write_config8(dev, 0x42, 0);
-}
-
-static void enable_shadow_ram(void)
-{
- device_t dev = 0; /* no need to look up 0:0.0 */
- unsigned char shadowreg;
- /* dev 0 for southbridge */
- shadowreg = pci_read_config8(dev, 0x63);
- /* 0xf0000-0xfffff */
- shadowreg |= 0x30;
- pci_write_config8(dev, 0x63, shadowreg);
-}
-
-static void main(unsigned long bist)
-{
- unsigned long x;
-
- if (bist == 0) {
- early_mtrr_init();
- }
- enable_vt8231_serial();
- uart_init();
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- /* init_timer();*/
- outb(5, 0x80);
-
- enable_mainboard_devices();
- enable_smbus();
- enable_shadow_ram();
- /* Check all of memory */
-#if 0
- ram_check(0x00000000, msr.lo);
-#endif
-#if 0
- static const struct {
- unsigned long lo, hi;
- } check_addrs[] = {
- /* Check 16MB of memory @ 0*/
- { 0x00000000, 0x01000000 },
-#if TOTAL_CPUS > 1
- /* Check 16MB of memory @ 2GB */
- { 0x80000000, 0x81000000 },
-#endif
- };
- int i;
- for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
- ram_check(check_addrs[i].lo, check_addrs[i].hi);
- }
-#endif
-}
Index: src/mainboard/densitron/dpx114/chip.h
===================================================================
--- src/mainboard/densitron/dpx114/chip.h (Revision 2680)
+++ src/mainboard/densitron/dpx114/chip.h (Arbeitskopie)
@@ -1,5 +0,0 @@
-extern struct chip_operations mainboard_densitron_dpx114_ops;
-
-struct mainboard_densitron_dpx114_config {
- int nothing;
-};
Index: src/mainboard/densitron/dpx114/cmos.layout
===================================================================
--- src/mainboard/densitron/dpx114/cmos.layout (Revision 2680)
+++ src/mainboard/densitron/dpx114/cmos.layout (Arbeitskopie)
@@ -1,74 +0,0 @@
-entries
-
-#start-bit length config config-ID name
-#0 8 r 0 seconds
-#8 8 r 0 alarm_seconds
-#16 8 r 0 minutes
-#24 8 r 0 alarm_minutes
-#32 8 r 0 hours
-#40 8 r 0 alarm_hours
-#48 8 r 0 day_of_week
-#56 8 r 0 day_of_month
-#64 8 r 0 month
-#72 8 r 0 year
-#80 4 r 0 rate_select
-#84 3 r 0 REF_Clock
-#87 1 r 0 UIP
-#88 1 r 0 auto_switch_DST
-#89 1 r 0 24_hour_mode
-#90 1 r 0 binary_values_enable
-#91 1 r 0 square-wave_out_enable
-#92 1 r 0 update_finished_enable
-#93 1 r 0 alarm_interrupt_enable
-#94 1 r 0 periodic_interrupt_enable
-#95 1 r 0 disable_clock_updates
-#96 288 r 0 temporary_filler
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-385 1 e 4 last_boot
-386 1 e 1 ECC_memory
-388 4 r 0 reboot_bits
-392 3 e 5 baud_rate
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-416 4 e 7 boot_first
-420 4 e 7 boot_second
-424 4 e 7 boot_third
-428 4 h 0 boot_index
-432 8 h 0 boot_countdown
-1008 16 h 0 check_sum
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Network
-7 1 HDD
-7 2 Floppy
-7 8 Fallback_Network
-7 9 Fallback_HDD
-7 10 Fallback_Floppy
-#7 3 ROM
-
-checksums
-
-checksum 392 1007 1008
-
-
Index: src/mainboard/densitron/dpx114/mainboard.c
===================================================================
--- src/mainboard/densitron/dpx114/mainboard.c (Revision 2680)
+++ src/mainboard/densitron/dpx114/mainboard.c (Arbeitskopie)
@@ -1,7 +0,0 @@
-#include <device/device.h>
-#include "chip.h"
-
-struct chip_operations mainboard_densitron_dpx114_ops = {
- CHIP_NAME("Densitron DPX114 Mainboard")
-};
-
Index: src/northbridge/transmeta/tm5800/Config.lb
===================================================================
--- src/northbridge/transmeta/tm5800/Config.lb (Revision 2680)
+++ src/northbridge/transmeta/tm5800/Config.lb (Arbeitskopie)
@@ -1,4 +0,0 @@
-
-config chip.h
-object northbridge.o
-
Index: src/northbridge/transmeta/tm5800/cpu_rev.c
===================================================================
--- src/northbridge/transmeta/tm5800/cpu_rev.c (Revision 2680)
+++ src/northbridge/transmeta/tm5800/cpu_rev.c (Arbeitskopie)
@@ -1,15 +0,0 @@
-/* this is a shrunken cpuid. */
-
-static unsigned int cpuid(unsigned int op)
-{
- unsigned int ret;
- unsigned dummy2,dummy3,dummy4;
-
- asm volatile (
- "cpuid"
- : "=a" (ret), "=b" (dummy2), "=c" (dummy3), "=d" (dummy4)
- : "a" (op)
- );
-
- return ret;
-}
Index: src/northbridge/transmeta/tm5800/debug.c
===================================================================
--- src/northbridge/transmeta/tm5800/debug.c (Revision 2680)
+++ src/northbridge/transmeta/tm5800/debug.c (Arbeitskopie)
@@ -1,70 +0,0 @@
-/*
- * generic K8 debug code, used by mainboard specific auto.c
- *
- */
-
-static void print_debug_pci_dev(unsigned dev)
-{
- print_debug("PCI: ");
- print_debug_hex8((dev >> 16) & 0xff);
- print_debug_char(':');
- print_debug_hex8((dev >> 11) & 0x1f);
- print_debug_char('.');
- print_debug_hex8((dev >> 8) & 7);
-}
-
-static void print_pci_devices(void)
-{
- device_t dev;
- for(dev = PCI_DEV(0, 0, 0);
- dev <= PCI_DEV(0, 0x1f, 0x7);
- dev += PCI_DEV(0,0,1)) {
- uint32_t id;
- id = pci_read_config32(dev, PCI_VENDOR_ID);
- if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0x0000)) {
- continue;
- }
- print_debug_pci_dev(dev);
- print_debug("\r\n");
- }
-}
-
-static void dump_pci_device(unsigned dev)
-{
- int i;
- print_debug_pci_dev(dev);
- print_debug("\r\n");
-
- for(i = 0; i <= 255; i++) {
- unsigned char val;
- if ((i & 0x0f) == 0) {
- print_debug_hex8(i);
- print_debug_char(':');
- }
- val = pci_read_config8(dev, i);
- print_debug_char(' ');
- print_debug_hex8(val);
- if ((i & 0x0f) == 0x0f) {
- print_debug("\r\n");
- }
- }
-}
-
-static void dump_pci_devices(void)
-{
- device_t dev;
- for(dev = PCI_DEV(0, 0, 0);
- dev <= PCI_DEV(0, 0x1f, 0x7);
- dev += PCI_DEV(0,0,1)) {
- uint32_t id;
- id = pci_read_config32(dev, PCI_VENDOR_ID);
- if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0x0000)) {
- continue;
- }
- dump_pci_device(dev);
- }
-}
Index: src/northbridge/transmeta/tm5800/northbridge.c
===================================================================
--- src/northbridge/transmeta/tm5800/northbridge.c (Revision 2680)
+++ src/northbridge/transmeta/tm5800/northbridge.c (Arbeitskopie)
@@ -1,155 +0,0 @@
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/hypertransport.h>
-#include <stdlib.h>
-#include <string.h>
-#include <bitops.h>
-#include "chip.h"
-#include "northbridge.h"
-
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
- struct resource *resource;
- unsigned reg;
-
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
- resource->limit = 0xffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
-static void ram_resource(device_t dev, unsigned long index,
- unsigned long basek, unsigned long sizek)
-{
- struct resource *resource;
-
- if (!sizek) {
- return;
- }
- resource = new_resource(dev, index);
- resource->base = ((resource_t)basek) << 10;
- resource->size = ((resource_t)sizek) << 10;
- resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-}
-
-static void tolm_test(void *gp, struct device *dev, struct resource *new)
-{
- struct resource **best_p = gp;
- struct resource *best;
- best = *best_p;
- if (!best || (best->base > new->base)) {
- best = new;
- }
- *best_p = best;
-}
-
-static uint32_t find_pci_tolm(struct bus *bus)
-{
- struct resource *min;
- uint32_t tolm;
- min = 0;
- search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
- tolm = 0xffffffffUL;
- if (min && tolm > min->base) {
- tolm = min->base;
- }
- return tolm;
-}
-
-static void pci_domain_set_resources(device_t dev)
-{
- struct resource *resource, *last;
- device_t mc_dev;
- uint32_t pci_tolm;
-
- pci_tolm = find_pci_tolm(&dev->link[0]);
- mc_dev = dev->link[0].children;
- if (mc_dev) {
- /* Figure out which areas are/should be occupied by RAM.
- * This is all computed in kilobytes and converted to/from
- * the memory controller right at the edges.
- * Having different variables in different units is
- * too confusing to get right. Kilobytes are good up to
- * 4 Terabytes of RAM...
- */
- unsigned long tomk, tolmk;
- int idx;
-
-#warning "This is hardcoded to 1MiB of RAM for now"
- tomk = 1024;
- /* Compute the top of Low memory */
- tolmk = pci_tolm >> 10;
- if (tolmk >= tomk) {
- /* The PCI hole does does not overlap the memory.
- */
- tolmk = tomk;
- }
- /* Report the memory regions */
- idx = 10;
- ram_resource(dev, idx++, 0, 640);
- ram_resource(dev, idx++, 768, tolmk - 768);
- }
- assign_resources(&dev->link[0]);
-}
-
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
- max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
- return max;
-}
-
-static struct device_operations pci_domain_ops = {
- .read_resources = pci_domain_read_resources,
- .set_resources = pci_domain_set_resources,
- .enable_resources = enable_childrens_resources,
- .init = 0,
- .scan_bus = pci_domain_scan_bus,
-};
-
-static void cpu_bus_init(device_t dev)
-{
- initialize_cpus(&dev->link[0]);
-}
-
-static void cpu_bus_noop(device_t dev)
-{
-}
-
-static struct device_operations cpu_bus_ops = {
- .read_resources = cpu_bus_noop,
- .set_resources = cpu_bus_noop,
- .enable_resources = cpu_bus_noop,
- .init = cpu_bus_init,
- .scan_bus = 0,
-};
-
-static void enable_dev(struct device *dev)
-{
- struct device_path path;
-
- /* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
- dev->ops = &pci_domain_ops;
- pci_set_method(dev);
- }
- else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
- dev->ops = &cpu_bus_ops;
- }
-}
-
-struct chip_operations northbridge_transmeta_tm5800_control = {
- CHIP_NAME("Transmeta TM5800 Northbridge")
- .enable_dev = enable_dev,
-};
Index: src/northbridge/transmeta/tm5800/chip.h
===================================================================
--- src/northbridge/transmeta/tm5800/chip.h (Revision 2680)
+++ src/northbridge/transmeta/tm5800/chip.h (Arbeitskopie)
@@ -1,5 +0,0 @@
-struct northbridge_transmeta_tm5800_config
-{
-};
-
-extern struct chip_operations northbridge_transmeta_tm5800_control;
Index: src/northbridge/transmeta/tm5800/northbridge.h
===================================================================
--- src/northbridge/transmeta/tm5800/northbridge.h (Revision 2680)
+++ src/northbridge/transmeta/tm5800/northbridge.h (Arbeitskopie)
@@ -1,5 +0,0 @@
-#ifndef NORTHBRIDGE_TRANSMETA_TM58000_H
-#define NORTHBRIDGE_TRANSMETA_TM58000_H
-
-
-#endif /* NORTHBRIDGE_TRANSMETA_TM58000_H */
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