On Saturday 02 June 2007 10:25, Yu-ning Feng wrote: > Please check whether I have understood correctly. > > The processor lauches a cycle with address = 0xFFFF_FFF0. The north > bridge chipset explains this address. In this case, it signals the > read line and chip select line which connect the ROM device, and > select an address of the ROM device through PCI bus AD[31..8]. To the > north bridge, the ROM device is like a common BIOS ROM except that it > uses PCI bus to exchange information. Then the ROM device uses > AD[7..0] to send 1 byte of data back to the north bridge. That 1 byte > of data is a portion of the 1st instruction.
This could be a valid scenario, yes. Juergen -- linuxbios mailing list [email protected] http://www.linuxbios.org/mailman/listinfo/linuxbios
