On Thu, Jun 14, 2007 at 07:32:33PM +0200, Stefan Reinauer wrote: > * Uwe Hermann <[EMAIL PROTECTED]> [070607 20:35]: > > Also, I tried to split up the ACPI/SMBus code into two functions, > > even though both devices have the same PCI ID. Is this supposed to > > work? > > LinuxBIOS will only call one constructor per file.
One _list_ of constructors, right? But I guess it won't handle multiple
constructors in that list which apply to the _same_ PCI IDs?
But anyway...
> Can't you call both functions from the same constructor?
...this is the easiest solution, so I did it this way.
> > One issue needs to be resolved: Where/how do we set the config options
> > from config.h? In the dts? For now they seem to default to 0 (off),
> > thus the devices are not initialized (QEMU still boots for some reason).
>
> See Ron's posting from these days.
>
> Qemu needs no init. We do it for the sake of it and for the hope that it
> will some time emulate enough of the hw. (Its improving)
OK, then I'll leave the default values for another patch (or until we
have real hardware using one of the 82371XX southbridges).
> > + /* TODO: ISA DMA init? */
> > }
>
> DMA init is there why dont you just call it?
Done. I had some trouble in v2 with this, but that has other reasons, I guess.
> > + // TODO: Rename to ide_init() if it's not 82371EB specific?
>
> it is specific. So remove TODO
I should have been more precise. It's specific to the 82371XX series,
yes, but it's mostly the same for any of the 82371FB/SB/AB/EB/MB.
Fixed now.
> > + if (conf->ide0_enable) {
> > + /* Enable/disable UDMA/33 operation (primary IDE interface). */
> > + reg8 = pci_read_config8(dev, UDMACTL);
> > + if (conf->ide0_drive0_udma33_enable) {
> > + reg8 |= PSDE0;
> > + printk(BIOS_INFO, "Primary IDE, drive 0: UDMA/33 on\n");
> > + } else {
> > + reg8 &= ~(PSDE0);
> > + printk(BIOS_INFO, "Primary IDE, drive 0: UDMA/33
> > off\n");
> > + }
> > + if (conf->ide0_drive1_udma33_enable) {
> > + reg8 |= PSDE1;
> > + printk(BIOS_INFO, "Primary IDE, drive 1: UDMA/33 on\n");
> > + } else {
> > + reg8 &= ~(PSDE1);
> > + printk(BIOS_INFO, "Primary IDE, drive 1: UDMA/33
> > off\n");
> > + }
>
> Suggestion for code size: If you do
>
> printk(BIOS_INFO, "%s IDE, drive %d: UDMA/33 %s\n", "Primary", 1, "on");
>
> Without any other magic, the resulting code will be a lot smaller, since
> it only saves one main string, plus the words Primary/Secondary and
> on/off instead of a full string every time. gcc is great sometimes.
Nice, thanks.
> > + printk(BIOS_INFO, "SMBus controller enabled.\n");
>
> This should be DEBUG.
OK, done. Shall we make _all_ "FOO init" messages DEBUG?
Attached is a heavily updated patch which now also supports pretty
much _all_ of the 82371FB/SB/AB/EB/MB southbridges...
I also changed some 'int smbus_io = 0xfff0' (SMBus I/O Base) to
a #define in i82371eb.h, I don't see a reason to make this a local
variable. Is there any reason?
Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
Replace most of the Intel 82371EB code in v3 with configurable, documented, and more readable code, which now also supports all 82371XX series southbridges: 82371FB/SB/AB/EB/MB. I dropped some Linux Networx and Bitworks copyright lines, as the new code doesn't contain any of the code by those two companies anymore. Also, I split up the ACPI/SMBus code into two functions, even though both devices have the same PCI ID. Add the required PCI IDs to pci_ids.h (plus some register #defines) and use them in the code (instead of hardcoded PCI IDs and register indexes). One issue needs to be resolved: Where/how do we set the config options from config.h? In the dts? For now they seem to default to 0 (off), thus the devices are not initialized (QEMU still boots, though). Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]> Index: include/device/pci_ids.h =================================================================== --- include/device/pci_ids.h (Revision 354) +++ include/device/pci_ids.h (Arbeitskopie) @@ -146,6 +146,31 @@ /* Vendors and devices. Sort key: vendor first, device next. */ -#define PCI_VENDOR_ID_AMD 0x1022 +#define PCI_VENDOR_ID_AMD 0x1022 +#define PCI_VENDOR_ID_INTEL 0x8086 + +/* Intel 82441FX PCI and Memory Controller (PMC). */ +#define PCI_DEVICE_ID_INTEL_82441FX 0x1237 /* Used by QEMU */ + +/* Intel 82371FB PCI ISA IDE Xcelerator (PIIX) */ +#define PCI_DEVICE_ID_INTEL_82371FB_ISA 0x122e +#define PCI_DEVICE_ID_INTEL_82371FB_IDE 0x1230 + +/* Intel 82371SB PCI ISA IDE Xcelerator (PIIX3) */ +#define PCI_DEVICE_ID_INTEL_82371SB_ISA 0x7000 /* Used by QEMU */ +#define PCI_DEVICE_ID_INTEL_82371SB_IDE 0x7010 /* Used by QEMU */ +#define PCI_DEVICE_ID_INTEL_82371SB_UHCI 0x7020 + +/* Intel 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) + * + * The 82371AB/EB/MB (PIIX4/PIIX4E/PIIX4M) have the same PCI IDs and are + * mostly compatible. + */ +#define PCI_DEVICE_ID_INTEL_82371AB_ISA 0x7110 +#define PCI_DEVICE_ID_INTEL_82371AB_IDE 0x7111 +#define PCI_DEVICE_ID_INTEL_82371AB_UHCI 0x7112 +#define PCI_DEVICE_ID_INTEL_82371AB_SMBUS 0x7113 /* Same as ACPI */ +#define PCI_DEVICE_ID_INTEL_82371AB_ACPI 0x7113 /* Used by QEMU */ + #endif /* DEVICE_PCI_IDS_H */ Index: southbridge/intel/i82371eb/i82371eb.c =================================================================== --- southbridge/intel/i82371eb/i82371eb.c (Revision 354) +++ southbridge/intel/i82371eb/i82371eb.c (Arbeitskopie) @@ -1,9 +1,8 @@ /* * This file is part of the LinuxBIOS project. * - * Copyright (C) 2004 Linux Networx - * Copyright (C) 2005 Bitworks - * Copyright (C) 2007 Ronald G. Minnich + * Copyright (C) 2007 Ronald G. Minnich <[EMAIL PROTECTED]> + * Copyright (C) 2007 Uwe Hermann <[EMAIL PROTECTED]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,111 +19,370 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* + * Note: This code should support the Intel 82371FB/SB/AB/EB/MB southbridges. + */ + +/* TODO: Rename this file (and some variables) to i82371xx later. */ + +/* Datasheet: + * - Name: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR + * - URL: http://www.intel.com/design/intarch/datashts/290550.htm + * - PDF: http://download.intel.com/design/intarch/datashts/29055002.pdf + * - Date: April 1997 + * - Order Number: 290550-002 + */ + +/* Datasheet: + * - Name: 82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE Xcelerator + * Specification Update + * - URL: http://www.intel.com/design/chipsets/specupdt/297658.htm + * - PDF: http://download.intel.com/design/chipsets/specupdt/29765801.pdf + * - Date: March 1998 + * - Order Number: 297658-004 + */ + +/* Datasheet: + * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) + * (applies to 82371AB/EB/MB, a.k.a. PIIX4/PIIX4E/PIIX4M) + * - URL: http://www.intel.com/design/intarch/datashts/290562.htm + * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf + * - Date: April 1997 + * - Order Number: 290562-001 + */ + +/* Datasheet: + * - Name: 82371AB/EB/MB (PIIX4/PIIX4E/PIIX4M) Specification Update + * - URL: http://www.intel.com/design/chipsets/specupdt/297738.htm + * - PDF: http://www.intel.com/design/chipsets/specupdt/29773817.pdf + * - Date: January 2002 + * - Order Number: 297738-017 + */ + #include <types.h> +#include <io.h> +#include <string.h> #include <console.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_ids.h> #include <mc146818rtc.h> -#include <string.h> +#include <isa-dma.h> +#include "i82371eb.h" #include "config.h" -/* The plain PCI device uses the standard PCI operations. */ +/* + * TODO. + * + * @param dev The device to use. + */ +static void isa_init(struct device *dev) +{ + /* Initialize the real-time clock (RTC). */ + rtc_init(0); -/* TODO: bring in the rest of the v2 code for controlling IDE enable. - * This is just placeholder code for now + /* TODO: Select full ISA (instead of EIO)? Do all SBs support that? */ + + /* Initialize ISA DMA. */ + isa_dma_init(); +} + +/** + * Initialize the IDE controller. + * + * Depending on the configuration variables 'ide0_enable' and 'ide1_enable' + * enable or disable the primary and secondary IDE interface, respectively. + * + * Depending on the configuration variable 'ide_legacy_enable' enable or + * disable access to the legacy IDE ports and the PCI Bus Master IDE I/O + * registers. + * + * @param dev The device to use. */ +static void ide_init_enable(struct device *dev) +{ + u16 reg16; + struct southbridge_intel_i82371eb_config *conf; -static void i82371eb_isa_init(struct device *dev) + conf = dev->device_configuration; + + /* Enable/disable the primary IDE interface. */ + reg16 = pci_read_config16(dev, IDETIM_PRI); + reg16 = ONOFF(conf->ide0_enable, reg16, IDE_DECODE_ENABLE); + pci_write_config16(dev, IDETIM_PRI, reg16); + + printk(BIOS_INFO, "IDE: %s IDE interface %s\n", "Primary", + conf->ide0_enable ? "enabled" : "disabled"); + + /* Enable/disable the secondary IDE interface. */ + reg16 = pci_read_config16(dev, IDETIM_SEC); + reg16 = ONOFF(conf->ide1_enable, reg16, IDE_DECODE_ENABLE); + pci_write_config16(dev, IDETIM_SEC, reg16); + + printk(BIOS_INFO, "IDE: %s IDE interface %s\n", "Secondary", + conf->ide1_enable ? "enabled" : "disabled"); + + /* Enable access to the legacy IDE ports (both primary and secondary), + * and the PCI Bus Master IDE I/O registers. + * Only do this if at least one IDE interface is enabled. + */ + if (conf->ide0_enable || conf->ide1_enable) { + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 = ONOFF(conf->ide_legacy_enable, reg16, + (PCI_COMMAND_IO | PCI_COMMAND_MASTER)); + pci_write_config16(dev, PCI_COMMAND, reg16); + + printk(BIOS_INFO, "IDE: Access to legacy IDE ports %s\n", + conf->ide_legacy_enable ? "enabled" : "disabled"); + } +} + +/** + * Initialize the Ultra DMA/33 support of the IDE controller. + * + * Depending on the configuration variables 'ide0_drive0_udma33_enable', + * 'ide0_drive1_udma33_enable', 'ide1_drive0_udma33_enable', and + * 'ide1_drive1_udma33_enable' enable or disable Ultra DMA/33 support for + * the respective IDE controller and drive. + * + * @param dev The device to use. + */ +/* TODO: Use an #ifdef to reduce code size? */ +static void ide_init_udma33(struct device *dev) { - rtc_init(0); + u8 reg8; + struct southbridge_intel_i82371eb_config *conf; + + conf = dev->device_configuration; + + /* Enable/disable UDMA/33 operation (primary IDE interface). */ + if (conf->ide0_enable) { + reg8 = pci_read_config8(dev, UDMACTL); + reg8 = ONOFF(conf->ide0_drive0_udma33_enable, reg8, PSDE0); + reg8 = ONOFF(conf->ide0_drive1_udma33_enable, reg8, PSDE1); + pci_write_config8(dev, UDMACTL, reg8); + + printk(BIOS_INFO, "IDE: %s, drive %d: UDMA/33 %s\n", + "Primary IDE interface", 0, + conf->ide0_drive0_udma33_enable ? "on" : "off"); + printk(BIOS_INFO, "IDE: %s, drive %d: UDMA/33 %s\n", + "Primary IDE interface", 1, + conf->ide0_drive1_udma33_enable ? "on" : "off"); + } + + /* Enable/disable Ultra DMA/33 operation (secondary IDE interface). */ + if (conf->ide1_enable) { + reg8 = pci_read_config8(dev, UDMACTL); + reg8 = ONOFF(conf->ide1_drive0_udma33_enable, reg8, SSDE0); + reg8 = ONOFF(conf->ide1_drive1_udma33_enable, reg8, SSDE1); + pci_write_config8(dev, UDMACTL, reg8); + + printk(BIOS_INFO, "IDE: %s, drive %d: UDMA/33 %s\n", + "Secondary IDE interface", 0, + conf->ide1_drive0_udma33_enable ? "on" : "off"); + printk(BIOS_INFO, "IDE: %s, drive %d: UDMA/33 %s\n", + "Secondary IDE interface", 1, + conf->ide1_drive1_udma33_enable ? "on" : "off"); + } } -static void i82371eb_ide_init(struct device *dev) +/** + * IDE init for the Intel 82371FB/SB IDE controller. + * + * @param dev The device to use. + */ +static void ide_init_i82371fb_sb(struct device *dev) { - unsigned short c; + ide_init_enable(dev); +} - printk(BIOS_DEBUG, "Enabling IDE channel 1\n"); - c = pci_read_config16(dev, 0x40); - c |= 0x8000; - pci_write_config16(dev, 0x40, c); +/** + * IDE init for the Intel 82371AB/EB/MB IDE controller. + * + * @param dev The device to use. + */ +static void ide_init_i82371ab_eb_mb(struct device *dev) +{ + ide_init_enable(dev); + ide_init_udma33(dev); +} - printk(BIOS_DEBUG, "Enabling IDE channel 2\n"); - c = pci_read_config16(dev, 0x42); - c |= 0x8000; - pci_write_config16(dev, 0x42, c); +static void uhci_init(struct device *dev) +{ + /* TODO: No special init needed!? */ +} - printk(BIOS_INFO, "Enabling Legacy IDE\n"); - c = pci_read_config16(dev, 4); - c |= 1; - pci_write_config16(dev, 4, c); +static void smbus_init(struct device *dev) +{ + u8 reg8; + u16 reg16; + + /* Set the SMBus I/O base. */ + pci_write_config32(dev, SMBBA, SMBUS_IOBASE | 1); + + /* Enable the SMBus Controller Host Interface. */ + reg8 = pci_read_config8(dev, SMBHSTCFG); + reg8 |= SMB_HST_EN; + pci_write_config8(dev, SMBHSTCFG, reg8); + + /* Enable access to the SMBus I/O space. */ + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_IO; + pci_write_config16(dev, PCI_COMMAND, reg16); + + /* Clear any lingering errors, so the transaction will run. */ + /* TODO: Needed? */ + outb(inb(SMBUS_IOBASE + SMBHSTSTS), SMBUS_IOBASE + SMBHSTSTS); + + printk(BIOS_DEBUG, "SMBus controller enabled\n"); } -static void i82371eb_acpi_init(struct device *dev) +static void acpi_init(struct device *dev) { - int smbus_io, pm_io; - printk(BIOS_DEBUG, "Enabling SMBus.\n"); + u8 reg8; - smbus_io = 0xFFF0; + /* Set the PM I/O base. */ + pci_write_config32(dev, PMBA, PM_IOBASE | 1); - /* iobase addr */ - pci_write_config32(dev, 0x90, smbus_io | 1); - /* smbus enable */ - pci_write_config8(dev, 0xd2, (0x4 << 1) | 1); - /* iospace enable */ - pci_write_config16(dev, 0x4, 1); + /* Enable access to the PM I/O space. */ + reg8 = pci_read_config8(dev, PMREGMISC); + reg8 |= PCI_COMMAND_IO; + pci_write_config8(dev, PMREGMISC, reg8); - printk(BIOS_DEBUG, "Enable Power Management Functions\n"); - pm_io = 0xFF80; - /* iobase addr */ - pci_write_config32(dev, 0x40, pm_io | 1); + printk(BIOS_DEBUG, "Power management functions enabled\n"); +} - /* enable pm io address */ - pci_write_config8(dev, 0x80, 1); +/** + * Wrapper function to combine the SMBus/ACPI init into one function, + * as both devices have the same PCI IDs on the 82371AB/EB/MB. + */ +static void smbus_acpi_init(struct device *dev) +{ + smbus_init(dev); + acpi_init(dev); } -/* You can override or extend each operation as needed for the device. */ -static struct device_operations i82371eb_isa_ops_dev = { - .constructor = default_device_constructor, - .phase3_scan = 0, - .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, - .phase4_enable_disable = 0, - .phase5_enable_resources = pci_dev_enable_resources, - .phase6_init = i82371eb_isa_init, - .ops_pci = &pci_dev_ops_pci, +static struct device_operations i82371xx_isa_ops_dev = { + .constructor = default_device_constructor, + .phase3_scan = 0, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase4_enable_disable = 0, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = isa_init, + .ops_pci = 0, /* No subsystem IDs on 82371XX! */ }; -static struct device_operations i82371eb_ide_ops_dev = { - .constructor = default_device_constructor, - .phase3_scan = 0, - .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, - .phase4_enable_disable = 0, - .phase5_enable_resources = pci_dev_enable_resources, - .phase6_init = i82371eb_ide_init, - .ops_pci = &pci_dev_ops_pci, +/* IDE init for the Intel 82371FB/SB. */ +static struct device_operations i82371fb_sb_ide_ops_dev = { + .constructor = default_device_constructor, + .phase3_scan = 0, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase4_enable_disable = 0, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = ide_init_i82371fb_sb, + .ops_pci = 0, /* No subsystem IDs on 82371XX! */ }; -static struct device_operations i82371eb_acpi_ops_dev = { - .constructor = default_device_constructor, - .phase3_scan = 0, - .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, - .phase4_enable_disable = 0, - .phase5_enable_resources = pci_dev_enable_resources, - .phase6_init = i82371eb_acpi_init, - .ops_pci = &pci_dev_ops_pci, +/* IDE init for the Intel 82371AB/EB/MB. */ +static struct device_operations i82371ab_eb_mb_ide_ops_dev = { + .constructor = default_device_constructor, + .phase3_scan = 0, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase4_enable_disable = 0, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = ide_init_i82371ab_eb_mb, + .ops_pci = 0, /* No subsystem IDs on 82371XX! */ }; +static struct device_operations i82371xx_uhci_ops_dev = { + .constructor = default_device_constructor, + .phase3_scan = 0, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase4_enable_disable = 0, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = uhci_init, + .ops_pci = 0, /* No subsystem IDs on 82371XX! */ +}; + +static struct device_operations i82371xx_smbus_acpi_ops_dev = { + .constructor = default_device_constructor, + .phase3_scan = 0, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase4_enable_disable = 0, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = smbus_acpi_init, + .ops_pci = 0, /* No subsystem IDs on 82371XX! */ +}; + +/** + * Constructors for the Intel 82371FB/SB/AB/EB/MB. + * + * QEMU emulates an Intel 82371SB ISA bridge and IDE controller, but the + * SMBus/ACPI device is actually an Intel 82371AB/EB/MB. + */ struct constructor i82371eb_constructors[] = { + /* Intel 82371FB ISA */ {.id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = 0x8086,.device = 0x7000}}}, - &i82371eb_isa_ops_dev}, + .u = {.pci = {.vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371FB_ISA}}}, + .ops = &i82371xx_isa_ops_dev}, + + /* Intel 82371FB IDE */ {.id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = 0x8086,.device = 0x7010}}}, - &i82371eb_ide_ops_dev}, + .u = {.pci = {.vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371FB_IDE}}}, + .ops = &i82371fb_sb_ide_ops_dev}, + + /* Note: The Intel 82371FB doesn't have UHCI/SMBus/ACPI. */ + + /* Intel 82371SB ISA (used by QEMU) */ {.id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = 0x8086,.device = 0x7113}}}, - &i82371eb_acpi_ops_dev}, + .u = {.pci = {.vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371SB_ISA}}}, + .ops = &i82371xx_isa_ops_dev}, + + /* Intel 82371SB IDE (used by QEMU) */ + {.id = {.type = DEVICE_ID_PCI, + .u = {.pci = {.vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371SB_IDE}}}, + .ops = &i82371fb_sb_ide_ops_dev}, + + /* Intel 82371SB UHCI */ + {.id = {.type = DEVICE_ID_PCI, + .u = {.pci = {.vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371SB_UHCI}}}, + .ops = &i82371xx_uhci_ops_dev}, + + /* Note: The Intel 82371SB doesn't have SMBus/ACPI. */ + + /* Intel 82371AB/EB/MB ISA */ + {.id = {.type = DEVICE_ID_PCI, + .u = {.pci = {.vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371AB_ISA}}}, + .ops = &i82371xx_isa_ops_dev}, + + /* Intel 82371AB/EB/MB IDE */ + {.id = {.type = DEVICE_ID_PCI, + .u = {.pci = {.vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371AB_IDE}}}, + .ops = &i82371ab_eb_mb_ide_ops_dev}, + + /* Intel 82371AB/EB/MB UHCI */ + {.id = {.type = DEVICE_ID_PCI, + .u = {.pci = {.vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371AB_UHCI}}}, + .ops = &i82371xx_uhci_ops_dev}, + + /* Intel 82371AB/EB/MB SMBus/ACPI (used by QEMU) */ + {.id = {.type = DEVICE_ID_PCI, + .u = {.pci = {.vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371AB_SMBUS}}}, + .ops = &i82371xx_smbus_acpi_ops_dev}, + {.ops = 0}, }; Index: southbridge/intel/i82371eb/i82371eb.h =================================================================== --- southbridge/intel/i82371eb/i82371eb.h (Revision 0) +++ southbridge/intel/i82371eb/i82371eb.h (Revision 0) @@ -0,0 +1,62 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <[EMAIL PROTECTED]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H +#define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H + +/* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the + * 'reg' variable, otherwise it clears those bits. + * + * Examples: + * reg16 = ONOFF(conf->ide0_enable, reg16, (1 << 5)); + * reg16 = ONOFF(conf->ide0_enable, reg16, (FOO | BAR)); + */ +/* TODO: Move into some global header file? */ +#define ONOFF(cond,reg,bits) ((cond) ? ((reg) | (bits)) : ((reg) & ~(bits))) + +#define XBCS 0x4e /* X-Bus Chip Select register */ + +/* IDE */ +#define IDETIM_PRI 0x40 /* IDE timing register, primary channel */ +#define IDETIM_SEC 0x42 /* IDE timing register, secondary channel */ +#define UDMACTL 0x48 /* Ultra DMA/33 control register */ + +/* SMBus */ +#define SMBBA 0x90 /* SMBus Base Address */ +#define SMBHSTCFG 0xd2 /* SMBus Host Configuration */ +#define SMBHSTSTS 0x00 /* SMBus Host Status register */ + +/* Power management (ACPI) */ +#define PMBA 0x40 /* Power Management Base Address */ +#define PMREGMISC 0x80 /* Miscellaneous Power Management */ + +/* I/O Bases */ +#define SMBUS_IOBASE 0xfff0 +#define PM_IOBASE 0xff80 + +/* Bit definitions */ +#define SMB_HST_EN (1 << 0) /* Host Interface Enable */ +#define IDE_DECODE_ENABLE (1 << 15) /* IDE Decode Enable */ +#define PSDE0 (1 << 0) /* Primary Drive 0 UDMA/33 */ +#define PSDE1 (1 << 1) /* Primary Drive 1 UDMA/33 */ +#define SSDE0 (1 << 2) /* Secondary Drive 0 UDMA/33 */ +#define SSDE1 (1 << 3) /* Secondary Drive 1 UDMA/33 */ + +#endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */ Index: southbridge/intel/i82371eb/config.h =================================================================== --- southbridge/intel/i82371eb/config.h (Revision 354) +++ southbridge/intel/i82371eb/config.h (Arbeitskopie) @@ -1,9 +1,7 @@ /* * This file is part of the LinuxBIOS project. * - * Copyright (C) 2004 Linux Networx - * Copyright (C) 2005 Bitworks - * Copyright (C) 2007 Ronald G. Minnich + * Copyright (C) 2007 Uwe Hermann <[EMAIL PROTECTED]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,11 +21,20 @@ #ifndef SOUTHBRIDGE_INTEL_I82371EB_CONFIG_H #define SOUTHBRIDGE_INTEL_I82371EB_CONFIG_H +#include <device/device.h> + +extern struct chip_operations southbridge_intel_i82371eb_ops; extern struct constructor i82371eb_constructors[]; struct southbridge_intel_i82371eb_config { - unsigned int ide0_enable : 1; - unsigned int ide1_enable : 1; + int ide0_enable:1; + int ide0_drive0_udma33_enable:1; + int ide0_drive1_udma33_enable:1; + int ide1_enable:1; + int ide1_drive0_udma33_enable:1; + int ide1_drive1_udma33_enable:1; + int ide_legacy_enable:1; + int usb_enable:1; /* TODO: Currently unused. */ }; -#endif /* SOUTHBRIDGE_INTEL_I82371EB_CONFIG_H */ +#endif /* SOUTHBRIDGE_INTEL_I82371EB_CONFIG_H */
signature.asc
Description: Digital signature
-- linuxbios mailing list [email protected] http://www.linuxbios.org/mailman/listinfo/linuxbios
