This patch fixes a number of comments and other issues raised by Peter.
More comments inline.
Peter Stuge wrote:
On Wed, Jun 27, 2007 at 11:07:10PM +0200, [EMAIL PROTECTED] wrote:
+++ LinuxBIOSv3/arch/x86/Makefile 2007-06-27 21:07:10 UTC (rev 387)
..
+$(obj)/arch/x86/geodelx/stage0.o: $(src)/arch/x86/geodelx/stage0.S
+ $(Q)mkdir -p $(obj)/arch/x86/geodelx
Uh? The rule depends on a file in a directory created in the rule?
+ $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n"
+ $(Q)$(CC) -E $(LINUXBIOSINCLUDE) $< \
+ -o $(obj)/arch/x86/stage0_asm.s -DBOOTBLK=0x1f00 \
+ -DRESRVED=0xf0 -DDATE=\"`date +%Y/%m/%d`\"
Maybe even the svn rev date?
+ /* Setup access to the cache for under 640K. Note MC not setup yet. */
+ msr.hi = 0x20000000;
+ msr.lo = 0xfff80;
+ wrmsr(MSR_GLIU0 + 0x20, msr);
+
+ msr.hi = 0x20000000;
+ msr.lo = 0x80fffe0;
+ wrmsr(MSR_GLIU0 + 0x21, msr);
+
+ msr.hi = 0x20000000;
+ msr.lo = 0xfff80;
+ wrmsr(MSR_GLIU1 + 0x20, msr);
+
+ msr.hi = 0x20000000;
+ msr.lo = 0x80fffe0;
+ wrmsr(MSR_GLIU1 + 0x21, msr);
No nice #defines around for these?
added defines for the MSRs and comments for the values.
+/**
+ * start_time1 Starts Timer 1 for port 61 use. FIXME try to figure
+ * out what these values mean.
+ */
+void start_timer1(void)
+{
+ outb(0x56, 0x43);
+ outb(0x12, 0x41);
+}
0x43 is PIT command/control.
0x41 is PIT counter 1.
0x56 means write counter 1 lower 8 bits in next IO, set the counter
mode to square wave generator (count down to 0 from programmed value
twice in a row, alternating the output signal) counting in 16-bit
binary mode.
0x12 is written to the counter.
Used for RAM refresh on XT/AT but the port 61 reference indicates it
has to do with the (emulated?) keyboard controller.
Good summary. Added to the function header with slight modifications.
+ msr_t msrGlcpSysRstpll;
This guy could use a better name. At least no caps.
changed to msr_glcp_sys_pll
+ msrGlcpSysRstpll.lo &=
+ ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
+ msrGlcpSysRstpll.lo |=
+ (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
Why 0xDE ?
Added comment - because AMD recommends setting based on stability testing
+ /* You should never get here..... The chip has reset. */
+ printk(BIOS_EMERG,"CONFIGURING PLL FAILURE -- HALT\n");
+ post_code(POST_PLL_RESET_FAIL);
+ __asm__ __volatile__("hlt\n");
How about that hlt() function? Remember we want to put panic room
code there when we have too much spare time.
I didn't change this. There was still some question about hlt() on the
list.
+/**
+ * Return the CPU clock rate. Rates in this system are always returned
+ * as multkiples of 33 Mhz.
+ *
+ */
+u32 cpu_speed(void)
Is there a doxygen syntax for the return value? Also please say which
unit the value is in. MHz?
done (I hope, I'm not doxygen guy)
+/**
+ * Return the Geode Link clock rate. Rates in this system are always
+ * returned as multkiples of 33 Mhz.
+ *
+ */
+u32 geode_link_speed(void)
Ditto.
ditto
+ speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) /
10;
+ if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) % 10)
> 5) {
Maybe that 0x1F is a #define?
done
+/**
+ * Return the PCI bus clock rate. Rates in this system are always
+ * returned as multkiples of 33 Mhz.
+ *
+ */
+u32 pci_speed(void)
Doxygen return value comment here too?
yup
+ msrnum = GLCP_DELAY_CONTROLS;
+ msr = rdmsr(msrnum);
+ if (msr.lo & ~(0x7C0)) {
+ return;
+ }
The juju must stay but 0x7c0 seems like a #define?
yup
+ if (spdbyte0 == 0 || spdbyte1 == 0) {
+ /* one dimm solution */
+ if (spdbyte1 == 0) {
+ msr.hi |= 0x000800000;
+ }
+ spdbyte0 += spdbyte1;
+ if (spdbyte0 > 8) {
+ /* large dimm */
+ if (glspeed < 334) {
+ msr.hi |= 0x0837100AA;
+ msr.lo |= 0x056960004;
+ } else {
+ msr.hi |= 0x082710055;
+ msr.lo |= 0x056960004;
+ }
+ } else if (spdbyte0 > 4) {
+ /* medium dimm */
+ if (glspeed < 334) {
+ msr.hi |= 0x0837100AA;
+ msr.lo |= 0x056960004;
+ } else {
+ msr.hi |= 0x0827100AA;
+ msr.lo |= 0x056960004;
+ }
+ } else {
+ /* small dimm */
+ if (glspeed < 334) {
+ msr.hi |= 0x0837100FF;
+ msr.lo |= 0x056960004;
+ } else {
+ msr.hi |= 0x0827100FF;
+ msr.lo |= 0x056960004;
+ }
+ }
+ } else {
+ /* two dimm solution */
+ spdbyte0 += spdbyte1;
+ if (spdbyte0 > 24) {
+ /* huge dimms */
+ if (glspeed < 334) {
+ msr.hi |= 0x0B37100A5;
+ msr.lo |= 0x056960004;
+ } else {
+ msr.hi |= 0x0B2710000;
+ msr.lo |= 0x056960004;
+ }
+ } else if (spdbyte0 > 16) {
+ /* large dimms */
+ if (glspeed < 334) {
+ msr.hi |= 0x0B37100A5;
+ msr.lo |= 0x056960004;
+ } else {
+ msr.hi |= 0x0B27100A5;
+ msr.lo |= 0x056960004;
+ }
+ } else if (spdbyte0 >= 8) {
+ /* medium dimms */
+ if (glspeed < 334) {
+ msr.hi |= 0x0937100A5;
+ msr.lo |= 0x056960004;
+ } else {
+ msr.hi |= 0x0C27100A5;
+ msr.lo |= 0x056960004;
+ }
+ } else {
+ /* small dimms */
+ if (glspeed < 334) {
+ msr.hi |= 0x0837100A5;
+ msr.lo |= 0x056960004;
+ } else {
+ msr.hi |= 0x082710000;
+ msr.lo |= 0x056960004;
+ }
+ }
Each if statements just changes a few bits. Couldn't this be made
more readable?
seemed like it was enough code change that this would get it's own patch
. I think I can get this done tomorrow
+DCacheSetupBad:
+ hlt /* Issues */
+ jmp DCacheSetupBad
Hehe, yes, we have issues. Should we aim for panic room code in
assembly?
+lout:
+ /* Restore the BIST result. */
+ movl %ebp, %eax
+ /* We need to set ebp? No need. */
+ movl %esp, %ebp
+ pushl %eax /* BIST */
+ call stage1_main
+ /* We will not go back. */
I remember commenting on this before; please handle a return or
change it to a jmp. (I like the latter.)
fixed in a prior patch
+fixed_mtrr_msr:
+ .long 0x250, 0x258, 0x259
+ .long 0x268, 0x269, 0x26A
+ .long 0x26B, 0x26C, 0x26D
+ .long 0x26E, 0x26F
+var_mtrr_msr:
+ .long 0x200, 0x201, 0x202, 0x203
+ .long 0x204, 0x205, 0x206, 0x207
..or this would be executed on return..
//Peter
Marc
--
Marc Jones
Senior Software Engineer
(970) 226-9684 Office
mailto:[EMAIL PROTECTED]
http://www.amd.com/embeddedprocessors
Clean up comments and #defines in Geode LX code.
Signed-off-by: Marc Jones <[EMAIL PROTECTED]>
Index: LinuxBIOSv3/arch/x86/geodelx/geodelx.c
===================================================================
--- LinuxBIOSv3.orig/arch/x86/geodelx/geodelx.c 2007-07-02 11:23:59.000000000
-0600
+++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c 2007-07-02 16:27:43.000000000
-0600
@@ -40,8 +40,21 @@
*/
/**
- * start_time1 Starts Timer 1 for port 61 use. FIXME try to figure
- * out what these values mean.
+ * start_time1 Starts Timer 1 for port 61 use.
+ * 0x43 is PIT command/control.
+ * 0x41 is PIT counter 1.
+ *
+ * The command 0x56 means write counter 1 lower 8 bits in next IO,
+ * set the counter mode to square wave generator (count down to 0
+ * from programmed value twice in a row, alternating the output signal)
+ * counting in 16-bit binary mode.
+ *
+ * 0x12 is counter/timer 1 and signals the PIT to do a RAM refresh
+ * approximately every 15us written to the counter.
+ *
+ * The PIT typically generating 1.19318 MHz
+ * Timer 1 was used for RAM refresh on XT/AT and can be read on port61.
+ * Port61 is used by many timing loops for calibration.
*/
void start_timer1(void)
{
@@ -134,42 +147,44 @@
*/
void pll_reset(int manualconf, u32 pll_hi, u32 pll_lo)
{
- struct msr msrGlcpSysRstpll;
+ struct msr msr_glcp_sys_pll;
- msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
+ msr_glcp_sys_pll = rdmsr(GLCP_SYS_RSTPLL);
printk(BIOS_DEBUG,
- "_MSR GLCP_SYS_RSTPLL (%08x) value is: %08x:%08x\n",
msrGlcpSysRstpll.hi, msrGlcpSysRstpll.lo);
+ "_MSR GLCP_SYS_RSTPLL (%08x) value is: %08x:%08x\n",
msr_glcp_sys_pll.hi, msr_glcp_sys_pll.lo);
post_code(POST_PLL_INIT);
- if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
+ if (!(msr_glcp_sys_pll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
printk(BIOS_DEBUG,"Configuring PLL\n");
if (manualconf) {
post_code(POST_PLL_MANUAL);
/* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */
- msrGlcpSysRstpll.hi = pll_hi;
+ msr_glcp_sys_pll.hi = pll_hi;
/* Hold Count - how long we will sit in reset */
- msrGlcpSysRstpll.lo = pll_lo;
+ msr_glcp_sys_pll.lo = pll_lo;
} else {
/*automatic configuration (straps) */
post_code(POST_PLL_STRAP);
- msrGlcpSysRstpll.lo &=
+ /* Hold 0xDE*16clocks during reset. */
+ /* AMD recomended value for proper PLL reset.*/
+ msr_glcp_sys_pll.lo &=
~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
- msrGlcpSysRstpll.lo |=
+ msr_glcp_sys_pll.lo |=
(0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
- msrGlcpSysRstpll.lo &=
+ msr_glcp_sys_pll.lo &=
~(RSTPPL_LOWER_COREBYPASS_SET |
RSTPPL_LOWER_MBBYPASS_SET);
- msrGlcpSysRstpll.lo |=
+ msr_glcp_sys_pll.lo |=
RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET;
}
/* Use SWFLAGS to remember: "we've already been here" */
- msrGlcpSysRstpll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);
+ msr_glcp_sys_pll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);
/* "reset the chip" value */
- msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
- wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
+ msr_glcp_sys_pll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
+ wrmsr(GLCP_SYS_RSTPLL, msr_glcp_sys_pll);
/* You should never get here..... The chip has reset. */
printk(BIOS_EMERG,"CONFIGURING PLL FAILURE -- HALT\n");
@@ -183,9 +198,8 @@
/**
- * Return the CPU clock rate. Rates in this system are always returned
- * as multkiples of 33 Mhz.
- *
+ * Return the CPU clock rate from the PLL MSR.
+ * @return CPU speed in MHz
*/
u32 cpu_speed(void)
{
@@ -193,17 +207,16 @@
struct msr msr;
msr = rdmsr(GLCP_SYS_RSTPLL);
- speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) /
10;
- if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) %
10) > 5) {
+ speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) &
RSTPLL_UPPER_CPUMULT_MASK) + 1) * 333) / 10;
+ if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) &
RSTPLL_UPPER_CPUMULT_MASK) + 1) * 333) % 10) > 5) {
++speed;
}
return (speed);
}
/**
- * Return the Geode Link clock rate. Rates in this system are always
- * returned as multkiples of 33 Mhz.
- *
+ * Return the GeodeLink clock rate from the PLL MSR.
+ * @return GeodeLink speed in MHz
*/
u32 geode_link_speed(void)
{
@@ -211,8 +224,8 @@
struct msr msr;
msr = rdmsr(GLCP_SYS_RSTPLL);
- speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) /
10;
- if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) % 10)
> 5) {
+ speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) &
RSTPLL_UPPER_GLMULT_MASK) + 1) * 333) / 10;
+ if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) &
RSTPLL_UPPER_GLMULT_MASK) + 1) * 333) % 10) > 5) {
++speed;
}
return (speed);
@@ -220,9 +233,8 @@
/**
- * Return the PCI bus clock rate. Rates in this system are always
- * returned as multkiples of 33 Mhz.
- *
+ * Return the PCI bus clock rate from the PLL MSR.
+ * @return PCI speed in MHz
*/
u32 pci_speed(void)
{
@@ -295,7 +307,7 @@
*/
msrnum = GLCP_DELAY_CONTROLS;
msr = rdmsr(msrnum);
- if (msr.lo & ~(0x7C0)) {
+ if (msr.lo & ~(DELAY_LOWER_STATUS_MASK)) {
return;
}
Index: LinuxBIOSv3/arch/x86/geodelx/stage1.c
===================================================================
--- LinuxBIOSv3.orig/arch/x86/geodelx/stage1.c 2007-07-02 11:23:59.000000000
-0600
+++ LinuxBIOSv3/arch/x86/geodelx/stage1.c 2007-07-02 11:25:31.000000000
-0600
@@ -52,20 +52,20 @@
/* Setup access to the cache for under 640K. Note MC not setup yet. */
msr.hi = 0x20000000;
- msr.lo = 0xfff80;
- wrmsr(MSR_GLIU0 + 0x20, msr);
+ msr.lo = 0x000fff80; /* 0-0x7FFFF */
+ wrmsr(MSR_GLIU0_BASE1, msr);
msr.hi = 0x20000000;
- msr.lo = 0x80fffe0;
- wrmsr(MSR_GLIU0 + 0x21, msr);
+ msr.lo = 0x080fffe0; /* 0x80000-0x9FFFF */
+ wrmsr(MSR_GLIU0_BASE2, msr);
msr.hi = 0x20000000;
- msr.lo = 0xfff80;
- wrmsr(MSR_GLIU1 + 0x20, msr);
+ msr.lo = 0x000fff80; /* 0-0x7FFFF */
+ wrmsr(MSR_GLIU1_BASE1, msr);
msr.hi = 0x20000000;
- msr.lo = 0x80fffe0;
- wrmsr(MSR_GLIU1 + 0x21, msr);
+ msr.lo = 0x080fffe0; /* 0x80000-0x9FFFF */
+ wrmsr(MSR_GLIU0_BASE2, msr);
}
Index: LinuxBIOSv3/include/arch/x86/amd_geodelx.h
===================================================================
--- LinuxBIOSv3.orig/include/arch/x86/amd_geodelx.h 2007-07-02
11:23:59.000000000 -0600
+++ LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2007-06-29 11:59:44.000000000
-0600
@@ -354,10 +354,13 @@
#define GLCP_GLD_MSR_ERROR (MSR_GLCP + 0x2003)
#define GLCP_GLD_MSR_PM (MSR_GLCP + 0x2004)
#define GLCP_DELAY_CONTROLS (MSR_GLCP + 0x0F)
+#define DELAY_LOWER_STATUS_MASK 0x7C0
#define GLCP_SYS_RSTPLL (MSR_GLCP + 0x14)
/* R/W */
#define RSTPLL_UPPER_GLMULT_SHIFT 7
+#define RSTPLL_UPPER_GLMULT_MASK 0x1F
#define RSTPLL_UPPER_GLDIV_SHIFT 6
#define RSTPLL_UPPER_CPUMULT_SHIFT 1
+#define RSTPLL_UPPER_CPUMULT_MASK 0x1F
#define RSTPLL_UPPER_CPUDIV_SHIFT 0
#define RSTPLL_LOWER_SWFLAGS_SHIFT 26
#define RSTPLL_LOWER_SWFLAGS_MASK (0x03F <<
RSTPLL_LOWER_SWFLAGS_SHIFT)
--
linuxbios mailing list
[email protected]
http://www.linuxbios.org/mailman/listinfo/linuxbios
