Author: uwe
Date: 2007-07-10 21:44:22 +0200 (Tue, 10 Jul 2007)
New Revision: 443
Modified:
LinuxBIOSv3/southbridge/amd/cs5536/cs5536.c
LinuxBIOSv3/southbridge/amd/cs5536/cs5536.h
LinuxBIOSv3/southbridge/amd/cs5536/dts
LinuxBIOSv3/southbridge/amd/cs5536/smbus_initram.c
LinuxBIOSv3/southbridge/amd/cs5536/stage1.c
Log:
Various coding style fixes and cosmetics (trivial).
Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Uwe Hermann <[EMAIL PROTECTED]>
Modified: LinuxBIOSv3/southbridge/amd/cs5536/cs5536.c
===================================================================
--- LinuxBIOSv3/southbridge/amd/cs5536/cs5536.c 2007-07-10 14:38:01 UTC (rev
442)
+++ LinuxBIOSv3/southbridge/amd/cs5536/cs5536.c 2007-07-10 19:44:22 UTC (rev
443)
@@ -36,10 +36,10 @@
struct msrinit {
u32 msrnum;
- struct msr msr;
+ struct msr msr;
};
-/* Master Configuration Register for Bus Masters.*/
+/* Master configuration register for bus masters */
struct msrinit SB_MASTER_CONF_TABLE[] = {
{USB2_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}},
{ATA_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00048f000}},
@@ -48,9 +48,9 @@
{0, {0, 0}}
};
-/* 5536 Clock Gating*/
+/* CS5536 clock gating */
struct msrinit CS5536_CLOCK_GATING_TABLE[] = {
- /* MSR Setting*/
+ /* MSR Setting */
{GLIU_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}},
{GLPCI_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}},
{GLCP_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}},
@@ -67,23 +67,23 @@
struct acpiinit acpi_init_table[] = {
{ACPI_IO_BASE + 0x00, 0x01000000},
- {ACPI_IO_BASE + 0x08, 0},
- {ACPI_IO_BASE + 0x0C, 0},
- {ACPI_IO_BASE + 0x1C, 0},
- {ACPI_IO_BASE + 0x18, 0x0FFFFFFFF},
+ {ACPI_IO_BASE + 0x08, 0x00000000},
+ {ACPI_IO_BASE + 0x0C, 0x00000000},
+ {ACPI_IO_BASE + 0x1C, 0x00000000},
+ {ACPI_IO_BASE + 0x18, 0xFFFFFFFF},
{ACPI_IO_BASE + 0x00, 0x0000FFFF},
{PMS_IO_BASE + PM_SCLK, 0x000000E00},
- {PMS_IO_BASE + PM_SED, 0x000004601},
+ {PMS_IO_BASE + PM_SED, 0x000004601},
{PMS_IO_BASE + PM_SIDD, 0x000008C02},
- {PMS_IO_BASE + PM_WKD, 0x0000000A0},
+ {PMS_IO_BASE + PM_WKD, 0x0000000A0},
{PMS_IO_BASE + PM_WKXD, 0x0000000A0},
{0, 0}
};
struct FLASH_DEVICE {
- unsigned char fType; /* Flash type: NOR or NAND */
- unsigned char fInterface; /* Flash interface: I/O or Memory */
- unsigned long fMask; /* Flash size/mask */
+ unsigned char fType; /* Flash type: NOR or NAND */
+ unsigned char fInterface; /* Flash interface: I/O or memory */
+ unsigned long fMask; /* Flash size/mask */
};
struct FLASH_DEVICE FlashInitTable[] = {
@@ -101,8 +101,8 @@
};
/**
- * Program ACPI LBAR and initialize ACPI registers.
- */
+ * Program ACPI LBAR and initialize ACPI registers.
+ */
static void pm_chipset_init(void)
{
u32 val = 0;
@@ -112,47 +112,45 @@
val = 0x0E00; /* 1ms */
outl(val, port);
- /* PM_WKXD */
- /* Make sure bits[3:0]=0000b to clear the */
- /* saved Sx state */
+ /* PM_WKXD */
+ /* Make sure bits[3:0]=0000b to clear the saved Sx state. */
port = (PMS_IO_BASE + PM_WKXD);
val = 0x0A0; /* 5ms */
outl(val, port);
- /* PM_WKD */
+ /* PM_WKD */
port = (PMS_IO_BASE + PM_WKD);
outl(val, port);
- /* PM_SED */
+ /* PM_SED */
port = (PMS_IO_BASE + PM_SED);
val = 0x04601; /* 5ms, # of 3.57954MHz clock edges */
outl(val, port);
- /* PM_SIDD */
+ /* PM_SIDD */
port = (PMS_IO_BASE + PM_SIDD);
val = 0x08C02; /* 10ms, # of 3.57954MHz clock edges */
outl(val, port);
}
-/**
- * Flash LBARs need to be setup before VSA init so the PCI BARs have
- * correct size info. Call this routine only if flash needs to be
- * configured (don't call it if you want IDE).
- *
- */
+/**
+ * Flash LBARs need to be setup before VSA init so the PCI BARs have
+ * correct size info. Call this routine only if flash needs to be
+ * configured (don't call it if you want IDE).
+ */
static void chipset_flash_setup(void)
{
- struct msr msr;
int i;
+ struct msr msr;
int numEnabled = 0;
printk(BIOS_DEBUG, "chipset_flash_setup: Start\n");
for (i = 0; i < ARRAY_SIZE(FlashInitTable); i++) {
if (FlashInitTable[i].fType != FLASH_TYPE_NONE) {
printk(BIOS_DEBUG, "Enable CS%d\n", i);
- /* we need to configure the memory/IO mask */
+ /* We need to configure the memory/IO mask. */
msr = rdmsr(FlashPort[i]);
- msr.hi = 0; /* start with the "enabled" bit clear */
+ msr.hi = 0; /* Start with "enabled" bit clear. */
if (FlashInitTable[i].fType == FLASH_TYPE_NAND)
msr.hi |= 0x00000002;
else
@@ -162,30 +160,28 @@
else
msr.hi &= ~0x00000004;
msr.hi |= FlashInitTable[i].fMask;
- printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n",
FlashPort[i],
- msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n",
+ FlashPort[i], msr.hi, msr.lo);
wrmsr(FlashPort[i], msr);
- /* now write-enable the device */
+ /* Now write-enable the device. */
msr = rdmsr(MDD_NORF_CNTRL);
msr.lo |= (1 << i);
- printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n",
MDD_NORF_CNTRL,
- msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n",
+ MDD_NORF_CNTRL, msr.hi, msr.lo);
wrmsr(MDD_NORF_CNTRL, msr);
- /* update the number enabled */
+ /* Update the number enabled. */
numEnabled++;
}
}
-
printk(BIOS_DEBUG, "chipset_flash_setup: Finish\n");
-
}
/**
- * Use this in the event that you have a FLASH part instead of an IDE drive.
- *Run after VSA init to enable the flash PCI device header
- */
+ * Use this in the event that you have a FLASH part instead of an IDE drive.
+ * Run after VSA init to enable the flash PCI device header.
+ */
static void enable_ide_nand_flash_header(void)
{
/* Tell VSA to use FLASH PCI header. Not IDE header. */
@@ -193,19 +189,22 @@
outl(0xDEADBEEF, 0xCFC);
}
-#define RTC_CENTURY 0x32
+#define RTC_CENTURY 0x32
#define RTC_DOMA 0x3D
#define RTC_MONA 0x3E
/**
- * standard init function for the lpc bus. Sets up the "serial irq"
interrupt,
- * which is NOT the same as serial interrupt, and also enables DMA from
- * the LPC bus. Configures the PC clock, enables rtc and ISA DMA.
- * @param southbridge config structure
- */
+ * Standard init function for the LPC bus.
+ *
+ * Sets up the "serial irq" interrupt, which is NOT the same as serial
+ * interrupt, and also enables DMA from the LPC bus. Configures the PC clock,
+ * enables RTC and ISA DMA.
+ *
+ * @param sb Southbridge config structure.
+ */
static void lpc_init(struct southbridge_amd_cs5536_config *sb)
{
- struct msr msr;
+ struct msr msr;
if (sb->lpc_serirq_enable) {
msr.lo = sb->lpc_serirq_enable;
@@ -213,23 +212,23 @@
wrmsr(MDD_IRQM_LPC, msr);
if (sb->lpc_serirq_polarity) {
msr.lo = sb->lpc_serirq_polarity << 16;
- msr.lo |= (sb->lpc_serirq_mode << 6) | (1 << 7);
/* enable */
+ msr.lo |= (sb->lpc_serirq_mode << 6) | (1 << 7);
/* Enable */
msr.hi = 0;
wrmsr(MDD_LPC_SIRQ, msr);
}
}
- /* Allow DMA from LPC */
+ /* Allow DMA from LPC. */
msr = rdmsr(MDD_DMA_MAP);
msr.lo = 0x7777;
wrmsr(MDD_DMA_MAP, msr);
- /* enable the RTC/CMOS century byte at address 32h */
+ /* Enable the RTC/CMOS century byte at address 0x32. */
msr = rdmsr(MDD_RTC_CENTURY_OFFSET);
msr.lo = RTC_CENTURY;
wrmsr(MDD_RTC_CENTURY_OFFSET, msr);
- /* enable the RTC/CMOS day of month and month alarms */
+ /* Enable the RTC/CMOS day of month and month alarms. */
msr = rdmsr(MDD_RTC_DOMA_IND);
msr.lo = RTC_DOMA;
wrmsr(MDD_RTC_DOMA_IND, msr);
@@ -243,43 +242,42 @@
isa_dma_init();
}
-/**
- * Depending on settings in the config struct, enable COM1 or COM2 or both.
- * If the enable is NOT set, the UARTS are explicitly disabled, which is
required
- * if (e.g.) there is a superio attached that does COM1 or COM2.
- * @param southbridge config structure
- */
+/**
+ * Depending on settings in the config struct, enable COM1 or COM2 or both.
+ *
+ * If the enable is NOT set, the UARTs are explicitly disabled, which is
+ * required if (e.g.) there is a Super I/O attached that does COM1 or COM2.
+ *
+ * @param sb Southbridge config structure.
+ */
static void uarts_init(struct southbridge_amd_cs5536_config *sb)
{
- struct msr msr;
+ struct msr msr;
u16 addr = 0;
u32 gpio_addr;
struct device *dev;
- dev = dev_find_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
+ dev = dev_find_device(PCI_VENDOR_ID_AMD,
+ PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
- gpio_addr &= ~1; /* clear IO bit */
+ gpio_addr &= ~1; /* Clear I/O bit */
printk(BIOS_DEBUG, "GPIO_ADDR: %08X\n", gpio_addr);
- /* This could be extended to support IR modes */
+ /* This could be extended to support IR modes. */
/* COM1 */
if (sb->com1_enable) {
- /* Set the address */
+ /* Set the address. */
switch (sb->com1_address) {
case 0x3F8:
addr = 7;
break;
-
case 0x3E8:
addr = 6;
break;
-
case 0x2F8:
addr = 5;
break;
-
case 0x2E8:
addr = 4;
break;
@@ -288,42 +286,44 @@
msr.lo |= addr << 16;
wrmsr(MDD_LEG_IO, msr);
- /* Set the IRQ */
+ /* Set the IRQ. */
msr = rdmsr(MDD_IRQM_YHIGH);
msr.lo |= sb->com1_irq << 24;
wrmsr(MDD_IRQM_YHIGH, msr);
/* GPIO8 - UART1_TX */
- /* Set: Output Enable (0x4) */
+ /* Set: Output Enable (0x4) */
outl(GPIOL_8_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
/* Set: OUTAUX1 Select (0x10) */
outl(GPIOL_8_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
/* GPIO8 - UART1_RX */
- /* Set: Input Enable (0x20) */
+ /* Set: Input Enable (0x20) */
outl(GPIOL_9_SET, gpio_addr + GPIOL_INPUT_ENABLE);
- /* Set: INAUX1 Select (0x34) */
+ /* Set: INAUX1 Select (0x34) */
outl(GPIOL_9_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
- /* Set: GPIO 8 + 9 Pull Up (0x18) */
+ /* Set: GPIO 8 + 9 Pull Up (0x18) */
outl(GPIOL_8_SET | GPIOL_9_SET,
gpio_addr + GPIOL_PULLUP_ENABLE);
- /* enable COM1 */
- /* Bit 1 = device enable Bit 4 = allow access to the upper
banks */
+ /* Enable COM1.
+ *
+ * Bit 1 = device enable
+ * Bit 4 = allow access to the upper banks
+ */
msr.lo = (1 << 4) | (1 << 1);
msr.hi = 0;
wrmsr(MDD_UART1_CONF, msr);
-
} else {
- /* Reset and disable COM1 */
+ /* Reset and disable COM1. */
msr = rdmsr(MDD_UART1_CONF);
- msr.lo = 1; // reset
+ msr.lo = 1; /* Reset */
wrmsr(MDD_UART1_CONF, msr);
- msr.lo = 0; // disabled
+ msr.lo = 0; /* Disabled */
wrmsr(MDD_UART1_CONF, msr);
- /* Disable the IRQ */
+ /* Disable the IRQ. */
msr = rdmsr(MDD_LEG_IO);
msr.lo &= ~(0xF << 16);
wrmsr(MDD_LEG_IO, msr);
@@ -335,15 +335,12 @@
case 0x3F8:
addr = 7;
break;
-
case 0x3E8:
addr = 6;
break;
-
case 0x2F8:
addr = 5;
break;
-
case 0x2E8:
addr = 4;
break;
@@ -352,42 +349,44 @@
msr.lo |= addr << 20;
wrmsr(MDD_LEG_IO, msr);
- /* Set the IRQ */
+ /* Set the IRQ. */
msr = rdmsr(MDD_IRQM_YHIGH);
msr.lo |= sb->com2_irq << 28;
wrmsr(MDD_IRQM_YHIGH, msr);
/* GPIO3 - UART2_RX */
- /* Set: Output Enable (0x4) */
+ /* Set: Output Enable (0x4) */
outl(GPIOL_3_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
/* Set: OUTAUX1 Select (0x10) */
outl(GPIOL_3_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
/* GPIO4 - UART2_TX */
- /* Set: Input Enable (0x20) */
+ /* Set: Input Enable (0x20) */
outl(GPIOL_4_SET, gpio_addr + GPIOL_INPUT_ENABLE);
- /* Set: INAUX1 Select (0x34) */
+ /* Set: INAUX1 Select (0x34) */
outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
- /* Set: GPIO 3 + 3 Pull Up (0x18) */
+ /* Set: GPIO 3 + 3 Pull Up (0x18) */
outl(GPIOL_3_SET | GPIOL_4_SET,
gpio_addr + GPIOL_PULLUP_ENABLE);
- /* enable COM2 */
- /* Bit 1 = device enable Bit 4 = allow access to the upper
banks */
+ /* Enable COM2.
+ *
+ * Bit 1 = device enable
+ * Bit 4 = allow access to the upper banks
+ */
msr.lo = (1 << 4) | (1 << 1);
msr.hi = 0;
wrmsr(MDD_UART2_CONF, msr);
-
} else {
- /* Reset and disable COM2 */
+ /* Reset and disable COM2. */
msr = rdmsr(MDD_UART2_CONF);
- msr.lo = 1; // reset
+ msr.lo = 1; /* Reset */
wrmsr(MDD_UART2_CONF, msr);
- msr.lo = 0; // disabled
+ msr.lo = 0; /* Disabled */
wrmsr(MDD_UART2_CONF, msr);
- /* Disable the IRQ */
+ /* Disable the IRQ. */
msr = rdmsr(MDD_LEG_IO);
msr.lo &= ~(0xF << 20);
wrmsr(MDD_LEG_IO, msr);
@@ -396,51 +395,51 @@
#define HCCPARAMS 0x08
#define IPREG04 0xA0
- #define USB_HCCPW_SET (1 << 1)
+#define USB_HCCPW_SET (1 << 1)
#define UOCCAP 0x00
- #define APU_SET (1 << 15)
+#define APU_SET (1 << 15)
#define UOCMUX 0x04
#define PMUX_HOST 0x02
#define PMUX_DEVICE 0x03
- #define PUEN_SET (1 << 2)
+#define PUEN_SET (1 << 2)
#define UDCDEVCTL 0x404
- #define UDC_SD_SET (1 << 10)
+#define UDC_SD_SET (1 << 10)
#define UOCCTL 0x0C
- #define PADEN_SET (1 << 7)
+#define PADEN_SET (1 << 7)
-/**
- * Depending on settings in the config struct, manage USB setup.
- * @param southbridge config structure
- */
+/**
+ * Depending on settings in the config struct, manage USB setup.
+ *
+ * @param sb Southbridge config structure.
+ */
static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
{
u32 *bar;
- struct msr msr;
+ struct msr msr;
struct device *dev;
- dev = dev_find_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_EHCI, 0);
+ dev = dev_find_device(PCI_VENDOR_ID_AMD,
+ PCI_DEVICE_ID_AMD_CS5536_EHCI, 0);
if (dev) {
-
- /* Serial Short Detect Enable */
+ /* Serial short detect enable */
msr = rdmsr(USB2_SB_GLD_MSR_CONF);
msr.hi |= USB2_UPPER_SSDEN_SET;
wrmsr(USB2_SB_GLD_MSR_CONF, msr);
- /* write to clear diag register */
+ /* Write to clear diag register. */
wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG));
bar = (u32 *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- /* Make HCCPARAMS writeable */
+ /* Make HCCPARAMS writable. */
*(bar + IPREG04) |= USB_HCCPW_SET;
- /* ; EECP=50h, IST=01h, ASPC=1 */
+ /* EECP=50h, IST=01h, ASPC=1 */
*(bar + HCCPARAMS) = 0x00005012;
}
- dev = dev_find_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
+ dev = dev_find_device(PCI_VENDOR_ID_AMD,
+ PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
if (dev) {
bar = (u32 *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -459,155 +458,155 @@
}
}
- /* PBz#6466: If the UOC(OTG) device, port 4, is configured as a device,
- * then perform the following sequence:
- *
- * - set SD bit in DEVCTRL udc register
- * - set PADEN (former OTGPADEN) bit in uoc register
- * - set APU bit in uoc register */
+ /* PBz#6466: If the UOC(OTG) device, port 4, is configured as a
+ * device, then perform the following sequence:
+ * - Set SD bit in DEVCTRL udc register
+ * - Set PADEN (former OTGPADEN) bit in uoc register
+ * - Set APU bit in uoc register
+ */
if (sb->enable_USBP4_device) {
- dev = dev_find_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
+ dev = dev_find_device(PCI_VENDOR_ID_AMD,
+ PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
if (dev) {
- bar = (u32 *) pci_read_config32(dev,
- PCI_BASE_ADDRESS_0);
+ bar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
*(bar + UDCDEVCTL) |= UDC_SD_SET;
-
}
dev = dev_find_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
+ PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
if (dev) {
- bar = (u32 *) pci_read_config32(dev,
- PCI_BASE_ADDRESS_0);
+ bar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
*(bar + UOCCTL) |= PADEN_SET;
*(bar + UOCCAP) |= APU_SET;
}
}
- /* Disable virtual PCI UDC and OTG headers */
- dev = dev_find_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
+ /* Disable virtual PCI UDC and OTG headers. */
+ dev = dev_find_device(PCI_VENDOR_ID_AMD,
+ PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
if (dev) {
pci_write_config32(dev, 0x7C, 0xDEADBEEF);
}
- dev = dev_find_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
+ dev = dev_find_device(PCI_VENDOR_ID_AMD,
+ PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
if (dev) {
pci_write_config32(dev, 0x7C, 0xDEADBEEF);
}
}
/**
- * This function is in an odd place. We need to see about moving to it
geodelx.c
- * But for now, let's get things working and put a #warning in. This function
- * initializes a lot of nasty bits needed for phase 2. Can this function run
- * before vsm is set up, or is it required for vsm? The order here is a
little hard to
- * figure out.
- */
+ * This function initializes a lot of nasty bits needed for phase 2.
+ *
+ * Can this function run before vsm is set up, or is it required for vsm?
+ * The order here is a little hard to figure out.
+ *
+ * This function is in an odd place. We need to see about moving it to
+ * geodelx.c. But for now, let's get things working and put a #warning in.
+ */
void chipsetinit(void)
{
struct device *dev;
- struct msr msr;
+ struct msr msr;
u32 msrnum;
struct southbridge_amd_cs5536_config *sb;
struct msrinit *csi;
post_code(P80_CHIPSET_INIT);
- dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA,
0);
- if (! dev) {
- printk(BIOS_ERR, "%s: Could not find the south bridge!\n",
__FUNCTION__);
+ dev = dev_find_device(PCI_VENDOR_ID_AMD,
+ PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
+ if (!dev) {
+ printk(BIOS_ERR, "%s: Could not find the south bridge!\n",
+ __FUNCTION__);
return;
}
sb = (struct southbridge_amd_cs5536_config *)dev->device_configuration;
+
#if 0
- if (! IsS3Resume()) */
+ if (!IsS3Resume())
{
struct acpiinit *aci = acpi_init_table;
for (; aci->ioreg; aci++) {
outl(aci->regdata, aci->ioreg);
inl(aci->ioreg);
}
-
pm_chipset_init();
}
#endif
- /* set hd IRQ */
+ /* Set HD IRQ. */
outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
- /* Allow IO read and writes during a ATA DMA operation.
- * This could be done in the HD rom but
- * do it here for easier debugging.
+ /* Allow I/O reads and writes during a ATA DMA operation. This could
+ * be done in the HD ROM but do it here for easier debugging.
*/
msrnum = ATA_SB_GLD_MSR_ERR;
msr = rdmsr(msrnum);
msr.lo &= ~0x100;
wrmsr(msrnum, msr);
- /* Enable Post Primary IDE. */
+ /* Enable post primary IDE. */
msrnum = GLPCI_SB_CTRL;
msr = rdmsr(msrnum);
msr.lo |= GLPCI_CRTL_PPIDE_SET;
wrmsr(msrnum, msr);
csi = SB_MASTER_CONF_TABLE;
- for (; csi->msrnum; csi++) {
+ for (/* Nothing */; csi->msrnum; csi++) {
msr.lo = csi->msr.lo;
msr.hi = csi->msr.hi;
- wrmsr(csi->msrnum, msr); // MSR - see table above
+ wrmsr(csi->msrnum, msr); /* MSR - see table above */
}
- /* Flash BAR size Setup */
+ /* Flash BAR size setup. */
printk(BIOS_ERR, "%sDoing chipset_flash_setup()\n",
- sb->enable_ide_nand_flash == 1 ? "" : "Not ");
+ sb->enable_ide_nand_flash == 1 ? "" : "Not ");
if (sb->enable_ide_nand_flash == 1)
chipset_flash_setup();
- /* */
- /* Set up Hardware Clock Gating */
- /* */
+ /* Set up hardware clock gating. */
+ /* TODO: Why the extra block here? Can it be removed? */
{
csi = CS5536_CLOCK_GATING_TABLE;
- for (; csi->msrnum; csi++) {
+ for (/* Nothing */; csi->msrnum; csi++) {
msr.lo = csi->msr.lo;
msr.hi = csi->msr.hi;
- wrmsr(csi->msrnum, msr); // MSR - see table above
+ wrmsr(csi->msrnum, msr); /* MSR - see table above */
}
}
}
-/**
- * Depending on settings in the config struct, enable COM1 or COM2 or both.
- * If the enable is NOT set, the UARTS are explicitly disabled, which is
required
- * if (e.g.) there is a superio attached that does COM1 or COM2.
- * @param southbridge config structure
- */
+/**
+ * TODO.
+ *
+ * @param dev The device to use.
+ */
static void southbridge_init(struct device *dev)
{
struct southbridge_amd_cs5536_config *sb =
(struct southbridge_amd_cs5536_config *)dev->device_configuration;
+
/*
* struct device *gpiodev;
* unsigned short gpiobase = MDD_GPIO;
*/
printk(BIOS_ERR, "cs5536: %s\n", __FUNCTION__);
+
setup_i8259();
lpc_init(sb);
uarts_init(sb);
if (sb->enable_gpio_int_route) {
vr_write((VRC_MISCELLANEOUS << 8) + PCI_INT_AB,
- (sb->enable_gpio_int_route & 0xFFFF));
+ (sb->enable_gpio_int_route & 0xFFFF));
vr_write((VRC_MISCELLANEOUS << 8) + PCI_INT_CD,
- (sb->enable_gpio_int_route >> 16));
+ (sb->enable_gpio_int_route >> 16));
}
- printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n",
__FUNCTION__,
- sb->enable_ide_nand_flash);
+ printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n",
+ __FUNCTION__, sb->enable_ide_nand_flash);
if (sb->enable_ide_nand_flash == 1) {
enable_ide_nand_flash_header();
}
@@ -616,10 +615,10 @@
#warning Add back in unwanted VPCI support
#if 0
- /* disable unwanted virtual PCI devices */
+ /* Disable unwanted virtual PCI devices. */
for (i = 0; (i < MAX_UNWANTED_VPCI) && (0 != sb->unwanted_vpci[i]);
i++) {
printk(BIOS_DEBUG, "Disabling VPCI device: 0x%08X\n",
- sb->unwanted_vpci[i]);
+ sb->unwanted_vpci[i]);
outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8);
outl(0xDEADBEEF, 0xCFC);
}
@@ -630,32 +629,35 @@
{
printk(BIOS_ERR, "cs5536: Enter %s: dev is %p\n", __FUNCTION__, dev);
printk(BIOS_ERR, "cs5536: Exit %s: dev is %p\n", __FUNCTION__, dev);
-
}
-/**
- * A slightly different enable resources than the standard.
- * We grab control here as VSA has played in this chip as well.
- * @param southbridge config structure
- */
+/**
+ * A slightly different enable resources than the standard.
+ * We grab control here as VSA has played in this chip as well.
+ *
+ * @param dev The device to use.
+ */
static void cs5536_pci_dev_enable_resources(struct device *dev)
{
+ /* TODO: Shouldn't this be BIOS_SPEW? */
printk(BIOS_ERR, "cs5536: %s()\n", __FUNCTION__);
pci_dev_enable_resources(dev);
enable_childrens_resources(dev);
}
static struct device_operations southbridge_ops = {
- .phase3_scan = scan_static_bus,
- .phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
- .phase5_enable_resources = cs5536_pci_dev_enable_resources,
- .phase6_init = southbridge_init,
+ .phase3_scan = scan_static_bus,
+ .phase4_read_resources = pci_dev_read_resources,
+ .phase4_set_resources = pci_dev_set_resources,
+ .phase5_enable_resources = cs5536_pci_dev_enable_resources,
+ .phase6_init = southbridge_init,
};
struct constructor cs5536_constructors[] = {
- {.id = {.type = DEVICE_ID_PCI,
- .u = {.pci = {.vendor = PCI_VENDOR_ID_AMD,.device =
PCI_DEVICE_ID_AMD_CS5536_ISA}}},
- .ops = &southbridge_ops},
- {.ops = 0},
+ {.id = {.type = DEVICE_ID_PCI,
+ .u = {.pci = {.vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_AMD_CS5536_ISA}}},
+ .ops = &southbridge_ops},
+
+ {.ops = 0},
};
Modified: LinuxBIOSv3/southbridge/amd/cs5536/cs5536.h
===================================================================
--- LinuxBIOSv3/southbridge/amd/cs5536/cs5536.h 2007-07-10 14:38:01 UTC (rev
442)
+++ LinuxBIOSv3/southbridge/amd/cs5536/cs5536.h 2007-07-10 19:44:22 UTC (rev
443)
@@ -441,7 +441,7 @@
#define FLASH_IO_128B 0x0000FF80
#define FLASH_IO_256B 0x0000FF00
-/* function prototypes */
+/* Function prototypes */
void cs5536_setup_extmsr(void);
void cs5536_setup_idsel(void);
void cs5536_usb_swapsif(void);
@@ -453,5 +453,4 @@
void cs5536_setup_onchipuart(void);
void cs5536_stage1(void);
-
-#endif /* SOUTHBRIDGE_AMD_CS5536_CS5536_H */
+#endif /* SOUTHBRIDGE_AMD_CS5536_CS5536_H */
Modified: LinuxBIOSv3/southbridge/amd/cs5536/dts
===================================================================
--- LinuxBIOSv3/southbridge/amd/cs5536/dts 2007-07-10 14:38:01 UTC (rev
442)
+++ LinuxBIOSv3/southbridge/amd/cs5536/dts 2007-07-10 19:44:22 UTC (rev
443)
@@ -27,7 +27,7 @@
/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
lpc_serirq_polarity = "0";
- /* 0:Continuous 1:Quiet */
+ /* 0:continuous 1:quiet */
lpc_serirq_mode = "0";
/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual PIC spec. */
Modified: LinuxBIOSv3/southbridge/amd/cs5536/smbus_initram.c
===================================================================
--- LinuxBIOSv3/southbridge/amd/cs5536/smbus_initram.c 2007-07-10 14:38:01 UTC
(rev 442)
+++ LinuxBIOSv3/southbridge/amd/cs5536/smbus_initram.c 2007-07-10 19:44:22 UTC
(rev 443)
@@ -333,10 +333,10 @@
/**
* Read a byte from the SPD.
*
- * For this chip, that is really just saying 'read a byte from smbus'.
- * So we use smbus_read_byte. Nota Bene: leave this here as a function
+ * For this chip, that is really just saying 'read a byte from SMBus'.
+ * So we use smbus_read_byte(). Nota Bene: leave this here as a function
* rather than a #define in an obscure location. This function is called
- * only a few dozen times, and it not performance critical.
+ * only a few dozen times, and it's not performance critical.
*
* @param device The device.
* @param address The address.
Modified: LinuxBIOSv3/southbridge/amd/cs5536/stage1.c
===================================================================
--- LinuxBIOSv3/southbridge/amd/cs5536/stage1.c 2007-07-10 14:38:01 UTC (rev
442)
+++ LinuxBIOSv3/southbridge/amd/cs5536/stage1.c 2007-07-10 19:44:22 UTC (rev
443)
@@ -41,11 +41,12 @@
*/
void cs5536_setup_extmsr(void)
{
- struct msr msr;
+ struct msr msr;
/* Forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM. */
msr.hi = msr.lo = 0x00000000;
+ /* TODO: unsigned char -> u8? */
#if CS5536_GLINK_PORT_NUM <= 4
msr.lo = CS5536_DEV_NUM <<
(unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8);
@@ -74,7 +75,7 @@
*/
void cs5536_usb_swapsif(void)
{
- struct msr msr;
+ struct msr msr;
msr = rdmsr(USB1_SB_GLD_MSR_CAP + 0x5);
@@ -97,7 +98,7 @@
*/
void cs5536_setup_iobase(void)
{
- struct msr msr;
+ struct msr msr;
/* Setup LBAR for SMBus controller. */
msr.hi = 0x0000f001;
@@ -126,16 +127,17 @@
}
/**
- * Power Button Setup.
+ * Power button setup.
*
* Setup GPIO24, it is the external signal for CS5536 vsb_work_aux which
- * controls all voltage rails except Vstandby & Vmem. We need to enable,
+ * controls all voltage rails except Vstandby & Vmem. We need to enable
* OUT_AUX1 and OUTPUT_ENABLE in this order.
*
* If GPIO24 is not enabled then soft-off will not work.
*/
void cs5536_setup_power_button(void)
{
+ /* TODO: Should be a #define? */
outl(0x40020000, PMS_IO_BASE + 0x40);
outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT);
outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
@@ -154,16 +156,12 @@
/* Setup GPIO pins 14/15 for SDA/SCL. */
val = GPIOL_15_SET | GPIOL_14_SET;
- /* Output Enable */
+ /* Output AUX1 + enable */
outl(val, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
-
- /* Output AUX1 */
outl(val, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
- /* Input Enable */
+ /* Input AUX1 + enable */
outl(val, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
-
- /* Input AUX1 */
outl(val, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
}
@@ -174,21 +172,21 @@
*/
void cs5536_disable_internal_uart(void)
{
- struct msr msr;
+ struct msr msr;
/* The UARTs default to enabled.
* Disable and reset them and configure them later (SIO init).
*/
msr = rdmsr(MDD_UART1_CONF);
- msr.lo = 1; // reset
+ msr.lo = 1; /* Reset */
wrmsr(MDD_UART1_CONF, msr);
- msr.lo = 0; // disabled
+ msr.lo = 0; /* Disable */
wrmsr(MDD_UART1_CONF, msr);
msr = rdmsr(MDD_UART2_CONF);
- msr.lo = 1; // reset
+ msr.lo = 1; /* Reset */
wrmsr(MDD_UART2_CONF, msr);
- msr.lo = 0; // disabled
+ msr.lo = 0; /* Disable */
wrmsr(MDD_UART2_CONF, msr);
}
@@ -201,7 +199,7 @@
*/
void cs5536_setup_cis_mode(void)
{
- struct msr msr;
+ struct msr msr;
/* Setup CPU interface serial to mode B to match CPU. */
msr = rdmsr(GLPCI_SB_CTRL);
@@ -211,16 +209,16 @@
}
/**
- * Enable the on chip UART.
+ * Enable the on-chip UART.
*
* See page 412 of the AMD Geode CS5536 Companion Device data book.
*/
void cs5536_setup_onchipuart(void)
{
- struct msr msr;
+ struct msr msr;
/* Setup early for polling only mode.
- * 1. Eanble GPIO 8 to OUT_AUX1, 9 to IN_AUX1.
+ * 1. Enable GPIO 8 to OUT_AUX1, 9 to IN_AUX1.
* GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34
* 2. Enable UART I/O space in MDD.
* MSR 0x51400014 bit 18:16
@@ -258,7 +256,7 @@
/**
* Board setup.
*
- * Known to work on the AMD Norwich and DIGITIAL-LOGIC boards.
+ * Known to work on the AMD Norwich and Advanced Digital Logic boards.
*
* The extmsr and cis_mode are common for sure. The RSTPLL check is mandatory.
* IDSEL of course is required, so the chip appears in PCI config space,
@@ -276,7 +274,7 @@
*/
void cs5536_stage1(void)
{
- struct msr msr;
+ struct msr msr;
/* Note: you can't do prints in here in most cases, and we don't want
* to hang on serial, so they are commented out.
--
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