Not much to say.
Marc
--
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:[EMAIL PROTECTED]
http://www.amd.com/embeddedprocessors
Add a POST_CODE marco to post_code.h and change all post_code() function calls
to POST_CODE macros.
Signed-off-by: Marc Jones <[EMAIL PROTECTED]>
Index: LinuxBIOSv3/arch/x86/archtables.c
===================================================================
--- LinuxBIOSv3.orig/arch/x86/archtables.c 2007-07-20 13:52:11.000000000
-0600
+++ LinuxBIOSv3/arch/x86/archtables.c 2007-07-20 13:57:36.000000000 -0600
@@ -25,6 +25,7 @@
#include <console.h>
#include <string.h>
#include <tables.h>
+#include <post_code.h>
//#include <cpu/cpu.h>
//#include <pirq_routing.h>
//#include <smp/mpspec.h>
@@ -77,7 +78,7 @@
low_table_start = 0;
low_table_end = 16;
- post_code(0x9a);
+ POST_CODE(0x9a);
/* This table must be betweeen 0xf0000 & 0x100000 */
// rom_table_end = write_pirq_routing_table(rom_table_end);
@@ -92,7 +93,7 @@
// rom_table_end = (rom_table_end+1023) & ~1023;
/* copy the smp block to address 0 */
- post_code(0x96);
+ POST_CODE(0x96);
/* The smp table must be in 0-1K, 639K-640K, or 960K-1M */
// new_low_table_end = write_smp_table(low_table_end);
Index: LinuxBIOSv3/arch/x86/geodelx/geodelx.c
===================================================================
--- LinuxBIOSv3.orig/arch/x86/geodelx/geodelx.c 2007-07-20 13:42:44.000000000
-0600
+++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c 2007-07-20 13:43:56.000000000
-0600
@@ -29,6 +29,7 @@
#include <amd_geodelx.h>
#include <spd.h>
#include <legacy.h>
+#include <post_code.h>
/* All these functions used to be in a lot of fiddly little files. To make it
* easier to find functions, we are merging them here. This file is our first
@@ -155,12 +156,12 @@
printk(BIOS_DEBUG,
"_MSR GLCP_SYS_RSTPLL (%08x) value is: %08x:%08x\n",
msr_glcp_sys_pll.hi, msr_glcp_sys_pll.lo);
- post_code(POST_PLL_INIT);
+ POST_CODE(POST_PLL_INIT);
if (!(msr_glcp_sys_pll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
printk(BIOS_DEBUG, "Configuring PLL\n");
if (manualconf) {
- post_code(POST_PLL_MANUAL);
+ POST_CODE(POST_PLL_MANUAL);
/* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */
msr_glcp_sys_pll.hi = pll_hi;
@@ -168,7 +169,7 @@
msr_glcp_sys_pll.lo = pll_lo;
} else {
/* Automatic configuration (straps) */
- post_code(POST_PLL_STRAP);
+ POST_CODE(POST_PLL_STRAP);
/* Hold 0xDE * 16 clocks during reset. AMD recomended
* value for PLL reset from silicon validation.
@@ -193,7 +194,7 @@
/* You should never get here... the chip has reset. */
printk(BIOS_EMERG, "CONFIGURING PLL FAILURE -- HALT\n");
- post_code(POST_PLL_RESET_FAIL);
+ POST_CODE(POST_PLL_RESET_FAIL);
hlt();
}
Index: LinuxBIOSv3/arch/x86/keyboard.c
===================================================================
--- LinuxBIOSv3.orig/arch/x86/keyboard.c 2007-07-20 13:53:38.000000000
-0600
+++ LinuxBIOSv3/arch/x86/keyboard.c 2007-07-20 13:56:29.000000000 -0600
@@ -2,12 +2,13 @@
#include <keyboard.h>
#include <device/device.h>
#include <io.h>
+#include <post_code.h>
static int kbd_empty_input_buffer(void)
{
unsigned long timeout;
for(timeout = 1000000; timeout && (inb(0x64) & 0x02); timeout--) {
- post_code(0);
+ POST_CODE(0);
}
return !!timeout;
}
@@ -16,7 +17,7 @@
{
unsigned long timeout;
for(timeout = 1000000; timeout && ((inb(0x64) & 0x01) == 0); timeout--)
{
- post_code(0);
+ POST_CODE(0);
}
return !!timeout;
}
Index: LinuxBIOSv3/arch/x86/pci_ops_auto.c
===================================================================
--- LinuxBIOSv3.orig/arch/x86/pci_ops_auto.c 2007-07-20 14:00:39.000000000
-0600
+++ LinuxBIOSv3/arch/x86/pci_ops_auto.c 2007-07-20 14:02:08.000000000 -0600
@@ -6,6 +6,7 @@
#include <device/pci_ops.h>
#include <types.h>
#include <io.h>
+#include <post_code.h>
/*
* Before we decide to use direct hardware access mechanisms, we try to do some
@@ -88,5 +89,5 @@
{
printk(BIOS_INFO, "Finding PCI configuration type.\n");
dev->ops->ops_pci_bus = pci_check_direct();
- post_code(0x5f);
+ POST_CODE(0x5f);
}
Index: LinuxBIOSv3/arch/x86/stage1.c
===================================================================
--- LinuxBIOSv3.orig/arch/x86/stage1.c 2007-07-20 13:30:57.000000000 -0600
+++ LinuxBIOSv3/arch/x86/stage1.c 2007-07-20 13:32:22.000000000 -0600
@@ -25,6 +25,7 @@
#include <tables.h>
#include <lib.h>
#include <mc146818rtc.h>
+#include <post_code.h>
#define UNCOMPRESS_AREA 0x60000
@@ -35,21 +36,16 @@
void hardware_stage1(void);
void disable_car(void);
-void post_code(u8 value)
-{
- outb(value, 0x80);
-}
-
static void stop_ap(void)
{
// nothing yet
- post_code(0xf0);
+ POST_CODE(0xf0);
}
static void enable_rom(void)
{
// nothing here yet
- post_code(0xf2);
+ POST_CODE(0xf2);
}
/*
@@ -74,7 +70,7 @@
mem->map[0].type = LB_MEM_RAM;
- post_code(0x02);
+ POST_CODE(0x02);
// before we do anything, we want to stop if we dont run
// on the bootstrap processor.
Index: LinuxBIOSv3/device/device.c
===================================================================
--- LinuxBIOSv3.orig/device/device.c 2007-07-20 13:48:18.000000000 -0600
+++ LinuxBIOSv3/device/device.c 2007-07-20 13:50:13.000000000 -0600
@@ -37,6 +37,7 @@
#include <string.h>
#include <lib.h>
#include <spinlock.h>
+#include <post_code.h>
/** Linked list of all devices. */
struct device *all_devices = &dev_root;
@@ -689,15 +690,15 @@
{
struct device *dev;
- post_code(0x31);
+ POST_CODE(0x31);
for (dev = all_devices; dev; dev = dev->next) {
if (dev->ops && dev->ops->phase1_set_device_operations) {
dev->ops->phase1_set_device_operations(dev);
}
}
- post_code(0x3e);
+ POST_CODE(0x3e);
printk(BIOS_DEBUG, "Phase 1: done\n");
- post_code(0x3f);
+ POST_CODE(0x3f);
}
/**
@@ -711,7 +712,7 @@
{
struct device *dev;
- post_code(0x41);
+ POST_CODE(0x41);
printk(BIOS_DEBUG, "Phase 2: Early setup...\n");
for (dev = all_devices; dev; dev = dev->next) {
printk(BIOS_SPEW, "%s: dev %s: ", __FUNCTION__, dev->dtsname);
@@ -724,9 +725,9 @@
printk(BIOS_SPEW, "\n");
}
- post_code(0x4e);
+ POST_CODE(0x4e);
printk(BIOS_DEBUG, "Phase 2: Done.\n");
- post_code(0x4f);
+ POST_CODE(0x4f);
}
/**
@@ -744,7 +745,7 @@
{
unsigned int new_max;
int do_phase3;
- post_code(0x42);
+ POST_CODE(0x42);
if (!busdevice || !busdevice->enabled ||
!busdevice->ops || !busdevice->ops->phase3_scan) {
printk(BIOS_INFO, "%s: %s: busdevice %p enabled %d ops %p\n",
@@ -776,7 +777,7 @@
}
}
}
- post_code(0x4e);
+ POST_CODE(0x4e);
printk(BIOS_INFO, "%s: returning %d\n", __FUNCTION__, max);
return new_max;
}
@@ -815,7 +816,7 @@
if (root->ops && root->ops->phase3_enable_scan) {
root->ops->phase3_enable_scan(root);
}
- post_code(0x41);
+ POST_CODE(0x41);
if (!root->ops) {
printk(BIOS_ERR,
"dev_root_phase3 missing 'ops' initialization\nPhase 3:
Failed.\n");
Index: LinuxBIOSv3/device/pci_device.c
===================================================================
--- LinuxBIOSv3.orig/device/pci_device.c 2007-07-20 13:50:33.000000000
-0600
+++ LinuxBIOSv3/device/pci_device.c 2007-07-20 13:51:30.000000000 -0600
@@ -30,6 +30,8 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <post_code.h>
+
#define CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT 0
#define CONFIG_PCIX_PLUGIN_SUPPORT 0
#define CONFIG_PCIE_PLUGIN_SUPPORT 0
@@ -1042,7 +1044,7 @@
__func__, old_devices, bus->dev, bus->dev->dtsname);
bus->children = 0;
- post_code(0x24);
+ POST_CODE(0x24);
printk(BIOS_SPEW, "PCI: scan devfn 0x%x to 0x%x\n", min_devfn,
max_devfn);
/* Probe all devices/functions on this bus with some optimization for
@@ -1075,7 +1077,7 @@
}
}
printk(BIOS_SPEW, "PCI: Done for loop\n");
- post_code(0x25);
+ POST_CODE(0x25);
/* Die if any leftover static devices are are found.
* There's probably a problem in the Config.lb.
@@ -1101,7 +1103,7 @@
* Return how far we've got finding sub-buses.
*/
printk(BIOS_DEBUG, "PCI: pci_scan_bus returning with max=%03x\n", max);
- post_code(0x55);
+ POST_CODE(0x55);
return max;
}
Index: LinuxBIOSv3/include/post_code.h
===================================================================
--- LinuxBIOSv3.orig/include/post_code.h 2007-07-20 13:26:32.000000000
-0600
+++ LinuxBIOSv3/include/post_code.h 2007-07-20 13:38:27.000000000 -0600
@@ -17,6 +17,8 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <io.h>
+#define POST_CODE(x) outb(x, 0x80)
#define POST_START_OF_MAIN 0x01
Index: LinuxBIOSv3/lib/elfboot.c
===================================================================
--- LinuxBIOSv3.orig/lib/elfboot.c 2007-07-20 13:34:35.000000000 -0600
+++ LinuxBIOSv3/lib/elfboot.c 2007-07-20 13:35:54.000000000 -0600
@@ -34,6 +34,7 @@
#include <tables.h>
#include <elf.h>
#include <elf_boot.h>
+#include <post_code.h>
static int valid_area(struct lb_memory *mem,
unsigned long start, unsigned long len)
@@ -151,7 +152,7 @@
//boot_successful();
printk(BIOS_DEBUG, "Jumping to boot code at 0x%x\n", entry);
- post_code(0xfe);
+ POST_CODE(0xfe);
/* Jump to kernel */
/* most of the time, jmp_to_elf_entry is just a call. But this hook
gives us
@@ -174,7 +175,7 @@
result = 0;
printk(BIOS_INFO, "ELF loader started.\n");
- post_code(0xf8);
+ POST_CODE(0xf8);
/* Scan for an elf header */
header_offset = -1;
@@ -214,7 +215,7 @@
printk(BIOS_ERR, "Cannot load ELF image\n");
- post_code(0xff);
+ POST_CODE(0xff);
}
return 0;
}
Index: LinuxBIOSv3/lib/stage2.c
===================================================================
--- LinuxBIOSv3.orig/lib/stage2.c 2007-07-20 13:45:42.000000000 -0600
+++ LinuxBIOSv3/lib/stage2.c 2007-07-20 13:47:52.000000000 -0600
@@ -27,6 +27,7 @@
#include <console.h>
#include <device/device.h>
#include <tables.h>
+#include <post_code.h>
/**
* Main function of the DRAM part of LinuxBIOS.
@@ -51,7 +52,7 @@
LINUXBIOS_BUILD
" booting...\n";
- post_code(0x20);
+ POST_CODE(0x20);
printk(BIOS_NOTICE, console_test);
@@ -60,7 +61,7 @@
/* Console init, also ANYTHING that has to be done
* before printk can be used.
*/
- post_code(0x30);
+ POST_CODE(0x30);
dev_phase1();
show_all_devs();
@@ -68,34 +69,34 @@
* done. This is for ANYTHING that might have to happen before
* device enumeration but that needs a printk.
*/
- post_code(0x40);
+ POST_CODE(0x40);
dev_phase2();
show_all_devs();
/* Walk physical devices and add any dynamic devices to the
* device tree.
*/
- post_code(0x30);
+ POST_CODE(0x30);
dev_root_phase3();
show_all_devs();
/* Compute and assign the bus resources. */
- post_code(0x40);
+ POST_CODE(0x40);
dev_phase4();
show_all_devs();
/* Now actually enable devices on the bus. */
- post_code(0x50);
+ POST_CODE(0x50);
dev_root_phase5();
show_all_devs();
/* Initialize devices on the bus. */
- post_code(0x60);
+ POST_CODE(0x60);
dev_phase6();
show_all_devs();
/* TODO: Add comment. */
- post_code(0x70);
+ POST_CODE(0x70);
write_tables();
show_all_devs();
Index: LinuxBIOSv3/mainboard/amd/norwich/initram.c
===================================================================
--- LinuxBIOSv3.orig/mainboard/amd/norwich/initram.c 2007-07-20
13:44:14.000000000 -0600
+++ LinuxBIOSv3/mainboard/amd/norwich/initram.c 2007-07-20 13:44:38.000000000
-0600
@@ -60,7 +60,7 @@
DIMM0, DIMM1
};
- post_code(POST_START_OF_MAIN);
+ POST_CODE(POST_START_OF_MAIN);
system_preinit();
Index: LinuxBIOSv3/mainboard/amd/norwich/stage1.c
===================================================================
--- LinuxBIOSv3.orig/mainboard/amd/norwich/stage1.c 2007-07-20
13:33:08.000000000 -0600
+++ LinuxBIOSv3/mainboard/amd/norwich/stage1.c 2007-07-20 13:33:46.000000000
-0600
@@ -32,7 +32,7 @@
void hardware_stage1(void)
{
- post_code(POST_START_OF_MAIN);
+ POST_CODE(POST_START_OF_MAIN);
geodelx_msr_init();
cs5536_stage1();
Index: LinuxBIOSv3/northbridge/amd/geodelx/geodelxinit.c
===================================================================
--- LinuxBIOSv3.orig/northbridge/amd/geodelx/geodelxinit.c 2007-07-20
14:02:30.000000000 -0600
+++ LinuxBIOSv3/northbridge/amd/geodelx/geodelxinit.c 2007-07-20
14:02:55.000000000 -0600
@@ -674,7 +674,7 @@
}
}
if (gl == 0) {
- post_code(POST_RCONFInitError);
+ POST_CODE(POST_RCONFInitError);
while (1); /* TODO: Should be hlt()? */
}
Index: LinuxBIOSv3/northbridge/amd/geodelx/raminit.c
===================================================================
--- LinuxBIOSv3.orig/northbridge/amd/geodelx/raminit.c 2007-07-20
13:38:57.000000000 -0600
+++ LinuxBIOSv3/northbridge/amd/geodelx/raminit.c 2007-07-20
13:42:23.000000000 -0600
@@ -58,7 +58,7 @@
spd_byte = smbus_read_byte(dimm, SPD_NUM_DIMM_BANKS);
if ((MIN_MOD_BANKS > spd_byte) && (spd_byte > MAX_MOD_BANKS)) {
printk(BIOS_EMERG, "Number of module banks not compatible\n");
- post_code(ERROR_BANK_SET);
+ POST_CODE(ERROR_BANK_SET);
hlt();
}
dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
@@ -66,7 +66,7 @@
spd_byte = smbus_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
if ((MIN_DEV_BANKS > spd_byte) && (spd_byte > MAX_DEV_BANKS)) {
printk(BIOS_EMERG, "Number of device banks not compatible\n");
- post_code(ERROR_BANK_SET);
+ POST_CODE(ERROR_BANK_SET);
hlt();
}
dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
@@ -74,7 +74,7 @@
if ((smbus_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
|| (smbus_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
printk(BIOS_EMERG, "Asymmetric DIMM not compatible\n");
- post_code(ERROR_UNSUPPORTED_DIMM);
+ POST_CODE(ERROR_UNSUPPORTED_DIMM);
hlt();
}
@@ -94,7 +94,7 @@
dimm_size = __builtin_ctz(dimm_size);
if (dimm_size > 8) { /* 8 is 1 GB only support 1 GB per DIMM */
printk(BIOS_EMERG, "Only support up to 1 GB per DIMM\n");
- post_code(ERROR_DENSITY_DIMM);
+ POST_CODE(ERROR_DENSITY_DIMM);
hlt();
}
dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
@@ -127,7 +127,7 @@
spd_byte = num_col_addr[smbus_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
if (spd_byte > MAX_COL_ADDR) {
printk(BIOS_EMERG, "DIMM page size not compatible\n");
- post_code(ERROR_SET_PAGE);
+ POST_CODE(ERROR_SET_PAGE);
hlt();
}
spd_byte -= 7;
@@ -175,7 +175,7 @@
#if 0
if (spd_byte0 < 0xA0 || spd_byte0 < 0xA0) {
printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink speed\n");
- post_code(POST_PLL_MEM_FAIL);
+ POST_CODE(POST_PLL_MEM_FAIL);
hlt();
}
#endif
@@ -191,7 +191,7 @@
/* Current speed > max speed? */
if (geode_link_speed() > speed) {
printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink speed\n");
- post_code(POST_PLL_MEM_FAIL);
+ POST_CODE(POST_PLL_MEM_FAIL);
hlt();
}
}
@@ -349,7 +349,7 @@
spd_byte = CASDDR[__builtin_ctz((u32) casmap0)];
} else {
printk(BIOS_EMERG, "DIMM CAS latencies not compatible\n");
- post_code(ERROR_DIFF_DIMMS);
+ POST_CODE(ERROR_DIFF_DIMMS);
hlt();
}
@@ -569,24 +569,24 @@
{
u8 spd_byte;
- post_code(POST_MEM_SETUP);
+ POST_CODE(POST_MEM_SETUP);
spd_byte = smbus_read_byte(dimm0, SPD_MODULE_ATTRIBUTES);
/* Check DIMM is not Registered and not Buffered DIMMs. */
if ((spd_byte != 0xFF) && (spd_byte & 3)) {
printk(BIOS_EMERG, "DIMM 0 NOT COMPATIBLE!\n");
- post_code(ERROR_UNSUPPORTED_DIMM);
+ POST_CODE(ERROR_UNSUPPORTED_DIMM);
hlt();
}
spd_byte = smbus_read_byte(dimm1, SPD_MODULE_ATTRIBUTES);
if ((spd_byte != 0xFF) && (spd_byte & 3)) {
printk(BIOS_EMERG, "DIMM 1 NOT COMPATIBLE!\n");
- post_code(ERROR_UNSUPPORTED_DIMM);
+ POST_CODE(ERROR_UNSUPPORTED_DIMM);
hlt();
}
- post_code(POST_MEM_SETUP2);
+ POST_CODE(POST_MEM_SETUP2);
/* Check that the memory is not overclocked. */
check_ddr_max(dimm0, dimm1);
@@ -595,13 +595,13 @@
* This is gross. It is an artifact of our move to parametes instead of
* #defines. FIXME! The fix is trivial but I want to see it work first.
*/
- post_code(POST_MEM_SETUP3);
+ POST_CODE(POST_MEM_SETUP3);
auto_size_dimm(dimm0, dimm0, dimm1);
- post_code(POST_MEM_SETUP4);
+ POST_CODE(POST_MEM_SETUP4);
auto_size_dimm(dimm1, dimm0, dimm1);
/* Set CAS latency. */
- post_code(POST_MEM_SETUP5);
+ POST_CODE(POST_MEM_SETUP5);
set_cas(dimm0, dimm1);
/* Set all the other latencies here (tRAS, tRP...). */
@@ -639,7 +639,7 @@
u32 i, msrnum;
struct msr msr;
- post_code(POST_MEM_ENABLE);
+ POST_CODE(POST_MEM_ENABLE);
/* Only enable MTest for TLA memory debug. */
/* EnableMTest(); */
@@ -653,7 +653,7 @@
((7 << CF07_UPPER_D1_PSZ_SHIFT) |
(7 << CF07_UPPER_D0_PSZ_SHIFT))) {
printk(BIOS_EMERG, "No memory in the system\n");
- post_code(ERROR_NO_DIMMS);
+ POST_CODE(ERROR_NO_DIMMS);
hlt();
}
@@ -768,7 +768,7 @@
wrmsr(msrnum, msr);
printk(BIOS_DEBUG, "DRAM controller init done.\n");
- post_code(POST_MEM_SETUP_GOOD);
+ POST_CODE(POST_MEM_SETUP_GOOD);
/* Make sure there is nothing stale in the cache. */
/* CAR stack is in the cache __asm__ __volatile__("wbinvd\n"); */
Index: LinuxBIOSv3/southbridge/amd/cs5536/cs5536.c
===================================================================
--- LinuxBIOSv3.orig/southbridge/amd/cs5536/cs5536.c 2007-07-20
14:03:19.000000000 -0600
+++ LinuxBIOSv3/southbridge/amd/cs5536/cs5536.c 2007-07-20 14:03:46.000000000
-0600
@@ -506,7 +506,7 @@
struct southbridge_amd_cs5536_config *sb;
struct msrinit *csi;
- post_code(P80_CHIPSET_INIT);
+ POST_CODE(P80_CHIPSET_INIT);
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
if (!dev) {
--
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