> 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f >--------------------------------------------------- >00: 86 80 20 71 06 01 80 20 03 00 00 06 00 00 00 00 >10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >50: 60 ff 0a 20 00 00 00 00 00 00 00 00 00 00 00 00 >60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >90: 00 00 da 77 00 00 00 00 00 00 00 00 00 00 00 00 >a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >f0: 00 00 00 00 00 00 00 00 00 00 00 00 08 00 00 00
- the refresh (offset 53h) should be 15,6µs instead of 7,8µs which should only be used for high density rams (>256MB) - CL, SRCD and SRP (offset 53h) are unconfigured. either read them from the spd or configure them by performing read/write tests - the onboard vga (offset 70h) is left unconfigured and thus disabling it - MISCC2 (offset 80h) is left unconfigured. the datasheet says for some bits: Do NOT program to 0. regarding the L2 cache on the cpu read the following: page 7: http://www.cs.inf.ethz.ch/stricker/lab/doc/intel-part4.pdf line 473ff http://fxr.watson.org/fxr/source/i386/i386/initcpu.c?v=RELENG4 Holger -- linuxbios mailing list [email protected] http://www.linuxbios.org/mailman/listinfo/linuxbios
