Quoting Tom Sylla <[EMAIL PROTECTED]>: > On 9/18/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote: > >> If you check out the pci_bus_enable_resources() function in >> pci_device.c i put these tests right before it calls the >> pci_dev_enable_resources() function. The tests were to clear the serr >> and parity error bits from Primary Device Status Register 0x06 and >> Secondary Status Register 0x1E. As you can see above the bits are not >> clearing from the Primary Device Status Register 0x06 and they are >> from the Secondary Status Register 0x1E. Then what happens is in the >> pci_dev_enable_resources() function it goes enable the serr and parity >> checking on the Command Register 0x04 and that is where it chokes. I >> am assuming it is because the bits are not clearing from the Primary >> Device Status Register 0x06. But, why won't it let me clear these >> bits? Note: On these bits your supposed to write a "1" to them to >> clear them back to 0. HELP?? > > Those bits *mean* something. You seem to be having parity or system > errors on that PCI segment. You need to figure out why. I assume that > with the factory BIOS you do not get serr or perr secondary status > reported? > So how do I go about finding out what is causing the parity error?? And why does the factory bios ignore this?
Thanks - Joe -- linuxbios mailing list [email protected] http://www.linuxbios.org/mailman/listinfo/linuxbios
