Hi, sorry for the delay.
On Tue, Oct 30, 2007 at 10:57:42PM -0400, Corey Osgood wrote:
> +#ifndef SOUTHBRIDGE_VIA_VT8237R_VT8237R_H
> +#define SOUTHBRIDGE_VIA_VT8237R_VT8237R_H
> +
> +/* Note: need to be moved into dts */
> +#define SMBUS_IO_BASE 0x0f00 //from award bios
> +#define PMIO_BASE 0x0500 //might as well set this while we're here
Yep, sounds like the correct location.
> +
> +#define SMBHSTSTAT SMBUS_IO_BASE + 0x0
Should probably be
#define SMBHSTSTAT (SMBUS_IO_BASE + 0x0)
(just in case; same for the other entries)
> +#define SMBSLVSTAT SMBUS_IO_BASE + 0x1
> +#define SMBHSTCTL SMBUS_IO_BASE + 0x2
> +#define SMBHSTCMD SMBUS_IO_BASE + 0x3
> +#define SMBXMITADD SMBUS_IO_BASE + 0x4
> +#define SMBHSTDAT0 SMBUS_IO_BASE + 0x5
> +
> +/* Define register settings */
> +#define HOST_RESET 0xff
> +#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states
> to READ
> +
> +#define SMBUS_TIMEOUT (100*1000*10)
> +
> +#define I2C_TRANS_CMD 0x40
> +#define CLOCK_SLAVE_ADDRESS 0x69
> +
> +#define SMBUS_DELAY() inb(0x80)
> +
> +
> +/* IDE specific bits */
> +#define IDE_MODE_REG 0x09
> +#define IDE0_NATIVE_MODE (1 << 0)
> +#define IDE1_NATIVE_MODE (1 << 2)
> +#define CHANNEL_ENABLE_REG 0x40
> +#define ENABLE_IDE0 (1 << 0)
> +#define ENABLE_IDE1 (1 << 1)
> +
> +/* These are default addresses according to Via */
> +/* Again, should really be in the dts, with a big warning "Don't touch
> unless
> + * you know what you're doing" */
> +#define IDE0_DATA_ADDR 0x1f0
> +#define IDE0_CONTROL_ADDR 0x3f4
> +#define IDE1_DATA_ADDR 0x170
> +#define IDE1_CONTROL_ADDR 0x370
Yes.
> +
> +/* By Award default, Via default is 0xCC0 */
> +#define BUS_MASTER_ADDR 0xfe00
> +
> +#endif /* SOUTHBRIDGE_VIA_VT8237R_VT8237R_H */
One note though: Please try to merge your VT8237R code/changes into v2
first. This file (and smbus_initram.c and maybe other files) seems to differ
in various (smaller or bigger) ways from the v2 code, and we should try to avoid
two diverging code-"streams" in v2/v3.
Please post a patch against v2 so we can get one "mainstream" working
version of the VT8237R code, then base your v3 port on the committed
v2 version.
> Index: southbridge/via/vt8237r/stage1.c
> ===================================================================
> --- southbridge/via/vt8237r/stage1.c (revision 0)
> +++ southbridge/via/vt8237r/stage1.c (revision 0)
> @@ -0,0 +1,26 @@
> +/*
> + * This file is part of the LinuxBIOS project.
> + *
> + * Copyright (C) 2007
Missing name.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> + */
> +
> +#include <types.h>
> +#include <lib.h>
> +
> +void vt8237r_stage1(void)
> +{
> + /* Nothing to do for the moment, but there will be later */
> +}
OK, but let's add the file later then. You can leave the Makefile
snippet for stage1.c in there (commented) for now.
> Index: southbridge/via/vt8237r/debug.c
> ===================================================================
> --- southbridge/via/vt8237r/debug.c (revision 0)
> +++ southbridge/via/vt8237r/debug.c (revision 0)
> @@ -0,0 +1,12 @@
> +static void dump_dev(device_t dev)
> +{
> + int i,j;
> +
> + for(i = 0; i < 256; i += 16) {
> + printk_debug("0x%x: ", i);
> + for(j = 0; j < 16; j++) {
> + printk_debug("%02x ", pci_read_config8(dev, i+j));
> + }
> + printk_debug("\n");
> + }
> +}
Nah, please drop this file. If it's really needed it should go in some
other *.c file here, or in some global place.
> Index: southbridge/via/vt8237r/dts
> ===================================================================
> --- southbridge/via/vt8237r/dts (revision 0)
> +++ southbridge/via/vt8237r/dts (revision 0)
> @@ -0,0 +1,35 @@
> +/*
> + * This file is part of the LinuxBIOS project.
> + *
> + * Copyright (C) 2007 Ronald G. Minnich <[EMAIL PROTECTED]>
Not quite, unless you got renamed recently ;)
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> + */
> +
> +{
> + constructor = "vt8237r_constructors";
> +
> + /* Interrupt enables for LPC bus. Each bit is an IRQ 0-15. */
> + lpc_serirq_enable = "0";
> +
> + /* LPC IRQ polarity. Each bit is an IRQ 0-15. */
> + lpc_serirq_polarity = "0";
> +
> + /* 0:continuous 1:quiet */
> + lpc_serirq_mode = "0";
> +
> + /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual PIC spec. */
> + enable_gpio_int_route = "0";
> +};
Yep, nice.
> Index: southbridge/via/vt8237r/Makefile
> ===================================================================
> --- southbridge/via/vt8237r/Makefile (revision 0)
> +++ southbridge/via/vt8237r/Makefile (revision 0)
> @@ -0,0 +1,28 @@
> +##
> +## This file is part of the LinuxBIOS project.
> +##
> +## Copyright (C) 2007 coresystems GmbH
> +## (Written by Stefan Reinauer <[EMAIL PROTECTED]> for coresystems GmbH)
Also not quite, but, well, doesn't really matter anyway.
> +##
> +## This program is free software; you can redistribute it and/or modify
> +## it under the terms of the GNU General Public License as published by
> +## the Free Software Foundation; either version 2 of the License, or
> +## (at your option) any later version.
> +##
> +## This program is distributed in the hope that it will be useful,
> +## but WITHOUT ANY WARRANTY; without even the implied warranty of
> +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +## GNU General Public License for more details.
> +##
> +## You should have received a copy of the GNU General Public License
> +## along with this program; if not, write to the Free Software
> +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> +##
> +
> +ifeq ($(CONFIG_SOUTHBRIDGE_VIA_VT8237R),y)
> +
> +STAGE2_CHIPSET_OBJ += $(obj)/southbridge/via/vt8237r/vt8237r.o
> +
> +STAGE0_CHIPSET_OBJ += $(obj)/southbridge/via/vt8237r/stage1.o
We have STAGE0 but stage1.o which will confuse everybody. Not related to
this patch, but we should fix it later...
> +
> +endif
> Index: southbridge/via/vt8237r/smbus_initram.c
> ===================================================================
> --- southbridge/via/vt8237r/smbus_initram.c (revision 0)
> +++ southbridge/via/vt8237r/smbus_initram.c (revision 0)
> @@ -0,0 +1,179 @@
> +/*
> + * This file is part of the LinuxBIOS project.
> + *
> + * Copyright (C) 2007 Corey Osgood <[EMAIL PROTECTED]>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> + */
> +
> +#include <types.h>
> +#include <console.h>
> +#include <io.h>
> +#include <device/pci.h>
> +#include "vt8237r.h"
See above, this file seems to diverge from what's in v2 currently.
> +
> +/**
> + * Enable the SMBus.
> + *
> + * Basically, set the enable bit in the controller. This can be (and is)
> + * called multiple times.
> + */
> +static void smbus_init(void)
> +{
> + struct device *dev;
> +
> + /* Power management controller */
> + /* This should work, but there are more important things to work on */
> + /* dev = PCI_DEV(0, 0x11, 0); */
> +
> + dev = dev_find_device(0x1106, 0x3227, 0);
> +
> + if (dev->device != 0x3227)
> + {
> + /* This won't display text if enable_smbus() is before serial
> init */
> + die("Power Managment Controller not found\n");
> + }
> +
> + /* Set clock source */
> + pci_write_config8(dev, 0x94, 0xa0);
> +
> + /* Write SMBus IO base to 0xd0 and enable SMBus */
> + pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1);
> +
> + /* Set to Award value */
> + pci_write_config8(dev, 0xd2, 0x01);
> +
> + /* Make it work for I/O ...*/
> + /* Note: the datasheet lists this register as read-only, but smbus
> + doesn't work without this. Weird... */
> + pci_write_config16(dev, 0x04, 0x0001);
> +
> + /* Set the power management IO base while we're here */
> + pci_write_config32(dev, 0x88, PMIO_BASE | 1 );
> +}
> +
> +static void smbus_print_error(unsigned char host_status_register, int loops)
> +{
> + /* Check if there actually was an error */
> + if ((!host_status_register || host_status_register == 0x40 ||
> + host_status_register == 0x42) && loops < SMBUS_TIMEOUT) return;
> +
> + printk(BIOS_ERR, "smbus_error: 0x%02x\n", host_status_register);
> + if (loops >= SMBUS_TIMEOUT) printk(BIOS_ERR, "SMBus Timout\n");
> + if (host_status_register & (1 << 4))
> + printk(BIOS_ERR, "Interrup/SMI# was Failed Bus Transaction\n");
> + if (host_status_register & (1 << 3)) printk(BIOS_ERR, "Bus Error\n");
> + if (host_status_register & (1 << 2)) printk(BIOS_ERR, "Device Error\n");
> + if (host_status_register & (1 << 1))
> + /* This isn't a real error... */
> + printk(BIOS_DEBUG, "Interrupt/SMI# was Successful
> Completion\n");
> + if (host_status_register & (1 << 0)) printk(BIOS_ERR, "Host Busy\n");
> +}
> +
> +/**
> + * Wait for the SMBus controller to become ready.
> + *
> + * This isn't quite as fancy as some functions, but it does the trick.
> + *
> + * @param smbus_io_base The SMBus I/O base.
> + */
> +static void smbus_wait(u16 smbus_io_base)
> +{
> + int loops;
> +
> + loops = 0;
> + /* Yes, this is a mess, but it's the easiest way to do it */
> + while ((inb(SMBHSTSTAT) & 1) && (loops <= SMBUS_TIMEOUT)) ++loops;
> + smbus_print_error(inb(SMBHSTSTAT), loops);
> +}
> +
> +static void smbus_reset(void)
> +{
> + outb(HOST_RESET, SMBHSTSTAT);
> + /* Datasheet says we have to read to take ownership of SMBus */
> + inb(SMBHSTSTAT);
> +}
> +
> +int smbus_read_byte(u32 device, u32 address)
> +{
> + u32 val;
> +
> + smbus_reset();
> + /* clear host data port */
> + outb(0x00, SMBHSTDAT0);
> + SMBUS_DELAY();
> + smbus_wait(SMBUS_IO_BASE);
> +
> + /* actual addr to reg format */
> + device = (device << 1);
> + device |= 1;
> + outb(device, SMBXMITADD);
> + outb(address, SMBHSTCMD);
> + /* start transaction, byte data read */
> + outb(0x48, SMBHSTCTL);
> +
> + SMBUS_DELAY();
> +
> + smbus_wait(SMBUS_IO_BASE);
> +
> + val = inb(SMBHSTDAT0);
> +
> + smbus_reset(); /* probably don't have to do this, but it can't
> hurt */
> + return val; /* can I just "return inb(SMBHSTDAT0)"? */
> +}
> +
> +
> +/**
> + * Read a byte from the SPD.
> + *
> + * For this chip, that is really just saying 'read a byte from SMBus'.
> + * So we use smbus_read_byte(). Nota Bene: leave this here as a function
> + * rather than a #define in an obscure location. This function is called
> + * only a few dozen times, and it's not performance critical.
> + *
> + * @param device The device.
> + * @param address The address.
> + * @return The data from the SMBus packet area or an error of 0xff (i.e. -1).
> + */
> +inline int spd_read_byte(u16 device, u8 address)
> +{
> + return smbus_read_byte(device, address);
> +}
> +
> +/**
> + * Read a few bytes from smbus to confirm it's working.
> + *
> + * On some systems, it may take a long (or very long) time for smbus to
> + * "warm up". This fixup will eventually cycle through possible dimm
> locations
> + * searching for a known bit of data, to confirm that smbus is ready to work.
> + *
> + * @param mem_controller The memory controller and spd addresses
> + */
> +static void smbus_fixup(void)
> +{
> + int i;
> + unsigned int byte = 0x00;
> + /* SMBus reads fail for ~22 reads without some fixup */
> + /* Read until we get the right data for a known byte */
> + /* This method has one major flaw: it needs DDR2 in DIMM0 */
> + printk(BIOS_DEBUG, "Waiting until SMBus ready");
> + for(i = 0; i < SMBUS_TIMEOUT && byte != 0x08; i++)
> + {
> + printk(BIOS_DEBUG, ".");
> + byte = smbus_read_byte(0xa0, 2); //ctrl->channel[0], 2);
> + }
> +
> + if (i >= SMBUS_TIMEOUT - 1) printk(BIOS_ERR, "-SMBus error!-\n");
> + else printk(BIOS_DEBUG, "Done!\n");
> +}
> Index: Kconfig
> ===================================================================
> --- Kconfig (revision 507)
> +++ Kconfig (working copy)
> @@ -74,16 +74,22 @@
> boolean
> config NORTHBRIDGE_INTEL_I440BXEMULATION
> boolean
> +config NORTHBRIDGE_VIA_CN700
> + boolean
>
> # Southbridges:
> config SOUTHBRIDGE_AMD_CS5536
> boolean
> config SOUTHBRIDGE_INTEL_I82371EB
> boolean
> +config SOUTHBRIDGE_VIA_VT8237R
> + boolean
>
> # Super I/Os:
> config SUPERIO_WINBOND_W83627HF
> boolean
> +config SUPERIO_FINTEK_F71805F
> + boolean
Yep.
>
> # Source all northbridge/southbridge/superio Kconfig files:
> source northbridge/intel/i440bxemulation/Kconfig
> Index: include/device/pci_ids.h
> ===================================================================
> --- include/device/pci_ids.h (revision 507)
> +++ include/device/pci_ids.h (working copy)
> @@ -152,6 +152,24 @@
> #define PCI_DEVICE_ID_AMD_CS5536_OTG 0x2097
> #define PCI_DEVICE_ID_AMD_CS5536_B0_IDE 0x209A
>
> +#define PCI_VENDOR_ID_VIA 0x1106
> +#define PCI_DEVICE_ID_CN700_0 0x0314
> +#define PCI_DEVICE_ID_CN700_1 0x1314
> +#define PCI_DEVICE_ID_CN700_2 0x2314
> +#define PCI_DEVICE_ID_CN700_3 0x3208
> +#define PCI_DEVICE_ID_CN700_4 0x4314
> +#define PCI_DEVICE_ID_CN700_7 0x7314
> +#define PCI_DEVICE_ID_CN700_BRIDGE 0xb198
> +#define PCI_DEVICE_ID_VT8237R_SATA 0x3149
> +#define PCI_DEVICE_ID_VT8237R_IDE 0x7111
> +#define PCI_DEVICE_ID_VT8237R_UHCI 0x3038
> +#define PCI_DEVICE_ID_VT8237R_EHCI 0x3104
> +#define PCI_DEVICE_ID_VT8237R_UDCI 0xd104
> +#define PCI_DEVICE_ID_VT8237R_LPC 0x3227
> +#define PCI_DEVICE_ID_VT8237R_AC97 0x3059
> +#define PCI_DEVICE_ID_VT8237R_MC97 0x3068
> +#define PCI_DEVICE_ID_VT8237R_LAN 0x3065
> +
> #define PCI_VENDOR_ID_CIRRUS 0x1013
> #define PCI_DEVICE_ID_CIRRUS_5446 0x00b8 /* Used by QEMU */
>
> Index: superio/fintek/f71805f/f71805f.h
> ===================================================================
> --- superio/fintek/f71805f/f71805f.h (revision 508)
> +++ superio/fintek/f71805f/f71805f.h (working copy)
> @@ -24,8 +24,10 @@
> * - URL: http://www.fintek.com.tw/eng/products.asp?BID=1&SID=17
> * - PDF: http://www.fintek.com.tw/files/productfiles/F71805F_V025.pdf
> * - Revision: V0.25P
> - */
> + */
>
> +void f71805f_enable_serial(u8, u8, u16);
> +
> /* Logical Device Numbers (LDN). */
> #define F71805F_FDC 0x00 /* Floppy */
> #define F71805F_SP1 0x01 /* UART1 */
> Index: mainboard/Kconfig
> ===================================================================
> --- mainboard/Kconfig (revision 507)
> +++ mainboard/Kconfig (working copy)
> @@ -47,12 +47,18 @@
> help
> Select this option for various system emulators, such as QEMU.
>
> +config VENDOR_JETWAY
> + bool "Jetway"
> + help
> + Select this for various systems from Jetway.
> +
> endchoice
>
> source "mainboard/adl/Kconfig"
> source "mainboard/amd/Kconfig"
> source "mainboard/artecgroup/Kconfig"
> source "mainboard/emulation/Kconfig"
> +source "mainboard/jetway/Kconfig"
>
> choice
> prompt "ROM chip size"
> Index: mainboard/jetway/Kconfig
> ===================================================================
> --- mainboard/jetway/Kconfig (revision 0)
> +++ mainboard/jetway/Kconfig (revision 0)
> @@ -0,0 +1,40 @@
> +##
> +## This file is part of the LinuxBIOS project.
> +##
> +## Copyright (C) 2007 coresystems GmbH
> +## (Written by Stefan Reinauer <[EMAIL PROTECTED]> for coresystems GmbH)
> +##
> +## This program is free software; you can redistribute it and/or modify
> +## it under the terms of the GNU General Public License as published by
> +## the Free Software Foundation; either version 2 of the License, or
> +## (at your option) any later version.
> +##
> +## This program is distributed in the hope that it will be useful,
> +## but WITHOUT ANY WARRANTY; without even the implied warranty of
> +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +## GNU General Public License for more details.
> +##
> +## You should have received a copy of the GNU General Public License
> +## along with this program; if not, write to the Free Software
> +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> +##
> +
> +choice
> + prompt "Mainboard model"
> + depends on VENDOR_JETWAY
> +
> +config BOARD_JETWAY_J7F2WE
> + bool "J7F2WE"
> + select ARCH_X86
> + select CPU_I586
> + select OPTION_TABLE
> + select NORTHBRIDGE_VIA_CN700
> + select SOUTHBRIDGE_VIA_VT8237R
> + select SUPERIO_FINTEK_F71805F
> + help
> + Jetway J7F2WE mainboard.
> +
> +endchoice
> +
> +source "mainboard/jetway/j7f2we/Kconfig"
> +
> Index: mainboard/jetway/j7f2we/Kconfig
> ===================================================================
> --- mainboard/jetway/j7f2we/Kconfig (revision 0)
> +++ mainboard/jetway/j7f2we/Kconfig (revision 0)
> @@ -0,0 +1,44 @@
> +##
> +## This file is part of the LinuxBIOS project.
> +##
> +## Copyright (C) 2007 coresystems GmbH
> +## (Written by Stefan Reinauer <[EMAIL PROTECTED]> for coresystems GmbH)
> +##
> +## This program is free software; you can redistribute it and/or modify
> +## it under the terms of the GNU General Public License as published by
> +## the Free Software Foundation; either version 2 of the License, or
> +## (at your option) any later version.
> +##
> +## This program is distributed in the hope that it will be useful,
> +## but WITHOUT ANY WARRANTY; without even the implied warranty of
> +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +## GNU General Public License for more details.
> +##
> +## You should have received a copy of the GNU General Public License
> +## along with this program; if not, write to the Free Software
> +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> +##
> +
> +config MAINBOARD_NAME
> + string
> + default jetway/j7f2we
> + depends BOARD_JETWAY_J7F2WE
> + help
> + This is the default mainboard name.
> +
> +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
> + hex
> + # TODO: Fix PCI ID.
> + default 0x1022
> + depends BOARD_JETWAY_J7F2WE
> + help
> + Mainboard specific PCI subsystem vendor ID.
> +
> +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
> + hex
> + # TODO: Fix PCI ID.
> + default 0x2323
> + depends BOARD_JETWAY_J7F2WE
> + help
> + Mainboard specific PCI subsystem device ID.
> +
> Index: mainboard/jetway/j7f2we/initram.c
> ===================================================================
> --- mainboard/jetway/j7f2we/initram.c (revision 0)
> +++ mainboard/jetway/j7f2we/initram.c (revision 0)
> @@ -0,0 +1,125 @@
> +/*
> + * This file is part of the LinuxBIOS project.
> + *
> + * Copyright (C) 2007 Advanced Micro Devices, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> + */
> +
> +#include <types.h>
> +#include <lib.h>
> +#include <console.h>
> +//#include <post_code.h>
> +#include <device/device.h>
> +#include <device/pci.h>
> +#include <string.h>
> +#include <io.h>
> +//#include <mtrr.h>
> +//#include "superio/fintek/f71805f/stage1.c"
> +#include "northbridge/via/cn700/raminit.h"
> +
> +/**
> + * Disable GP2 and GP3 on the vt8237r. If this isn't done, the system will
> + * reboot ~3 seconds after the initial powerup.
> + */
> +#if 0
> +static void mb_gpio_init(struct device *lpc_dev)
> +{
> + pci_write_config8(lpc_dev, 0x98, 0x00);
> +}
> +
> +/**
> + * enable_shadow_ram on the cn700. There are two sets of registers that
> + * control shadow ram, and they need to be kept in sync.
> + */
> +
> +static void enable_shadow_ram(const struct mem_controller *ctrl)
> +{
> + u8 shadowreg;
> +
> + printk(BIOS_DEBUG, "Enabling shadow ram\r\n");
> + /* Enable shadow ram as normal dram */
> + /* 0xc0000-0xcffff */
> + pci_write_config8(ctrl->d0f3, 0x80, 0xff);
> + pci_write_config8(ctrl->d0f7, 0x61, 0xff);
> + /* 0xd0000-0xdffff */
> + pci_write_config8(ctrl->d0f3, 0x81, 0xff);
> + pci_write_config8(ctrl->d0f7, 0x62, 0xff);
> + /* 0xe0000-0xeffff */
> + pci_write_config8(ctrl->d0f3, 0x82, 0xff);
> + pci_write_config8(ctrl->d0f7, 0x64, 0xff);
> +
> + /* 0xf0000-0xfffff */
> + shadowreg = pci_read_config8(ctrl->d0f3, 0x83);
> + shadowreg |= 0x30;
> + pci_write_config8(ctrl->d0f3, 0x83, 0x30);
> +
> + /* Do it again for the vlink controller */
> + shadowreg = pci_read_config8(ctrl->d0f7, 0x63);
> + shadowreg |= 0x30;
> + pci_write_config8(ctrl->d0f7, 0x63, 0x30);
> +}
> +
> +#endif
> +/**
> + * main for initram for the Jetway J7F2WE. Based heavily on my own v2 code.
> + */
> +int main(void)
> +{
> + //f71805f_enable_serial(0x2e, F71805F_SP2, 0x2f8);
> +#if 0
> + const struct mem_controller cn700[] = {
> + {
> + .d0f0 = dev_find_device(0x1106, 0x0314, 0),
Maybe use pci_ids.h #defines here, too.
> + .d0f1 = dev_find_device(0x1106, 0x1314, 0),
> + .d0f2 = dev_find_device(0x1106, 0x2314, 0),
> + .d0f3 = dev_find_device(0x1106, 0x3208, 0),
> + .d0f4 = dev_find_device(0x1106, 0x4314, 0),
> + .d0f7 = dev_find_device(0x1106, 0x7314, 0),
> + .d1f0 = dev_find_device(0x1106, 0xb198, 0),
> + },
> + };
> +
> + //post_code(POST_START_OF_MAIN);
> +
> + struct device *lpc_dev;
Move all variable definitions to the top of the function, please.
> + lpc_dev = dev_find_device(0x1106, 0x3227, 0);
pci_ids.h
> + mb_gpio_init(lpc_dev);
> +
> + //f71805f_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE);
> +
> + /* Allows access to all northbridge devices. */
> + pci_write_config8(cn700->d0f0, 0x4f, 0x01);
> +
> + if (lpc_dev->device != 0x3227) {
> + printk(BIOS_DEBUG, "Southbridge not found!!!\n\r");
> + } else {
> + //disable_sata(lpc_dev);
> + printk(BIOS_DEBUG, "Enabling mainboard devices\r\n");
> + //enable_mainboard_devices(lpc_dev);
> + }
> +
> + enable_shadow_ram(cn700);
> +
> + sdram_set_registers(cn700);
> + //sdram_set_spd_registers(cn700);
> + sdram_enable(cn700);
> + /* Check low memory */
> + //ram_check(0x00000000, 640*1024);
> + /* Check 32mb */
> + //ram_check(1024*1024, 32*1024*1024);
> +#endif
> + return 0;
> +}
> Index: mainboard/jetway/j7f2we/stage1.c
> ===================================================================
> --- mainboard/jetway/j7f2we/stage1.c (revision 0)
> +++ mainboard/jetway/j7f2we/stage1.c (revision 0)
> @@ -0,0 +1,40 @@
> +/*
> + * This file is part of the LinuxBIOS project.
> + *
> + * Copyright (C) 2007 Corey Osgood <[EMAIL PROTECTED]>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> + */
> +
> +#include <types.h>
> +#include <lib.h>
> +#include <console.h>
> +#include <post_code.h>
> +#include <device/device.h>
> +#include <device/pci.h>
> +#include <string.h>
> +#include <io.h>
> +#include <superio/fintek/f71805f/f71805f.h>
> +
> +#define SERIAL_DEV F71805F_SP2
Not needed, use F71805F_SP2 directly for now.
> +#define SERIAL_IOBASE 0x2f8
Yes, but both this and the COM2 LDN etc. etc. should all be in dts, I
think.
> +
> +void hardware_stage1(void)
> +{
> + post_code(POST_START_OF_MAIN);
> +
> + f71805f_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE);
> + printk(BIOS_DEBUG, "Done %s\n", __FUNCTION__);
> +}
> Index: mainboard/jetway/j7f2we/irq_tables.c
> ===================================================================
> --- mainboard/jetway/j7f2we/irq_tables.c (revision 0)
> +++ mainboard/jetway/j7f2we/irq_tables.c (revision 0)
IRQ tables should become part of dts too. No code support for that yet
I'm afraid, so I guess we'll have to keep the file around for now.
Or, as it's probably not successfully usable right now anyway, let's
add it later?
> @@ -0,0 +1,60 @@
> +/* This file was generated by getpir.c, do not modify!
> + (but if you do, please run checkpir on it to verify)
> + * Contains the IRQ Routing Table dumped directly from your memory, which
> BIOS sets up
> + *
> + * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
> +*/
Drop this, unneeded (and don't want a copy of it in each board).
> +
> +#include <arch/pirq_routing.h>
> +
> +#define ID_SLOT_PCI_NET 1 // ThinCan
> ethernet
> +#define ID_SLOT_PCI_RSVD1 2 // reserved entry 1
> +#define ID_SLOT_PCI_RSVD3 3 // reserved entry 2
> +#define ID_SLOT_PCI_RSVD2 4 // reserved entry 3
> +#define ID_EMBED_PCI 0xff // onboard PCI device
> +
> +// CS5535 PCI INT[A-D] Interrupt Routing lines.
> +#define NO_CONNECT 0 // not used
> +#define CS_PCI_INTA 1 // PCI INTA
> +#define CS_PCI_INTB 2 // PCI INTB
> +#define CS_PCI_INTC 3 // PCI INTC
> +#define CS_PCI_INTD 4 // PCI INTD
> +
> +// IRQ bitmap reference line FEDCBA9876543210
> +//
> 0000110000100000b
> +#define PCI_IRQ 0xc20 // PCI allowed
> IRQs here
> +
> +const struct irq_routing_table intel_irq_routing_table =
> +{
> + PIRQ_SIGNATURE, /* u32 signature */
> + PIRQ_VERSION, /* u16 version */
> + 32+16*6, /* there can be total 2 devices on the bus */
> + 0x00, /* Where the interrupt router lies (bus) */
> + (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
> + 0x0800, /* IRQs devoted exclusively to PCI usage */
> + 0x1022, /* Vendor */
> + 0x208f, /* Device */
> + 0x00000000, /* Crap (miniport) */
> + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
> + 0xdf, /* u8 checksum , this hase to set to some value that
> would give 0 after the sum of all bytes for this structure (including
> checksum) */
> + {
> + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link,
> bitmap}, {link, bitmap}, slot, rfu */
> + // Geode GX3 Host Bridge and VGA Graphics
> + {0, 0x01<<3, {{CS_PCI_INTA, PCI_IRQ}, {NO_CONNECT, PCI_IRQ},
> {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}}, ID_EMBED_PCI, 0x0},
> + // Realtek RTL8100/8139 Network Controller
> + {0, 0x0d<<3, {{CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ},
> {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}}, ID_SLOT_PCI_NET, 0x0},
> + // Reserved for future extensions
> + {0, 0x0c<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ},
> {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_SLOT_PCI_RSVD1, 0x0},
> + // Geode CS5535/CS5536 IO Companion: USB controllers, IDE,
> Audio.
> + {0, 0x0f<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ},
> {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_EMBED_PCI, 0x0},
> + // Reserved for future extensions
> + {0, 0x0e<<3, {{CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ},
> {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}}, ID_SLOT_PCI_RSVD2, 0x0},
> + // Reserved for future extensions
> + {0, 0x0b<<3, {{CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ},
> {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}}, ID_SLOT_PCI_RSVD3, 0x0}
> + }
> +};
> +
> +unsigned long write_pirq_routing_table(unsigned long addr)
> +{
> + return copy_pirq_routing_table(addr);
> +}
> Index: mainboard/jetway/j7f2we/dts
> ===================================================================
> --- mainboard/jetway/j7f2we/dts (revision 0)
> +++ mainboard/jetway/j7f2we/dts (revision 0)
> @@ -0,0 +1,46 @@
> +/*
> + * This file is part of the LinuxBIOS project.
> + *
> + * Copyright (C) 2007 Ronald G. Minnich <[EMAIL PROTECTED]>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> + */
> +
> +/{
> + mainboard-vendor = "Jetway";
> + mainboard-name = "J7F2WE";
> + enabled;
> + cpus {
> + enabled;
> + };
> + domain0 {
> + enabled;
> + pcidomain = "0";
> + device0,0 {
> + enabled;
> + pcipath = "1,0";
> + };
> + southbridge {
> + /config/("southbridge/via/vt8237r");
> + pcipath = "11,0";
> + enabled;
> + };
> + superio {
> + /config/("superio/fintek/f71805f");
> + com1enable = "1";
> + com2enable = "1";
> + };
> + };
> +};
> Index: mainboard/jetway/j7f2we/cmos.layout
> ===================================================================
> --- mainboard/jetway/j7f2we/cmos.layout (revision 0)
> +++ mainboard/jetway/j7f2we/cmos.layout (revision 0)
Let's leave this out for now. I'm not even sure we can handle these
files at the momen in v3, and the method _how_ we handle it might
also change.
It _might_ make sense to become a part of dts, but I'm not entirely
sure. The dts is mostly for hardware properties and config, not sure
if this can be considered as such? Comments, opinions?
> @@ -0,0 +1,74 @@
> +entries
> +
> +#start-bit length config config-ID name
> +#0 8 r 0 seconds
> +#8 8 r 0 alarm_seconds
> +#16 8 r 0 minutes
> +#24 8 r 0 alarm_minutes
> +#32 8 r 0 hours
> +#40 8 r 0 alarm_hours
> +#48 8 r 0 day_of_week
> +#56 8 r 0 day_of_month
> +#64 8 r 0 month
> +#72 8 r 0 year
> +#80 4 r 0 rate_select
> +#84 3 r 0 REF_Clock
> +#87 1 r 0 UIP
> +#88 1 r 0 auto_switch_DST
> +#89 1 r 0 24_hour_mode
> +#90 1 r 0 binary_values_enable
> +#91 1 r 0 square-wave_out_enable
> +#92 1 r 0 update_finished_enable
> +#93 1 r 0 alarm_interrupt_enable
> +#94 1 r 0 periodic_interrupt_enable
> +#95 1 r 0 disable_clock_updates
> +#96 288 r 0 temporary_filler
> +0 384 r 0 reserved_memory
> +384 1 e 4 boot_option
> +385 1 e 4 last_boot
> +386 1 e 1 ECC_memory
> +388 4 r 0 reboot_bits
> +392 3 e 5 baud_rate
> +400 1 e 1 power_on_after_fail
> +412 4 e 6 debug_level
> +416 4 e 7 boot_first
> +420 4 e 7 boot_second
> +424 4 e 7 boot_third
> +428 4 h 0 boot_index
> +432 8 h 0 boot_countdown
> +1008 16 h 0 check_sum
> +
> +enumerations
> +
> +#ID value text
> +1 0 Disable
> +1 1 Enable
> +2 0 Enable
> +2 1 Disable
> +4 0 Fallback
> +4 1 Normal
> +5 0 115200
> +5 1 57600
> +5 2 38400
> +5 3 19200
> +5 4 9600
> +5 5 4800
> +5 6 2400
> +5 7 1200
> +6 6 Notice
> +6 7 Info
> +6 8 Debug
> +6 9 Spew
> +7 0 Network
> +7 1 HDD
> +7 2 Floppy
> +7 8 Fallback_Network
> +7 9 Fallback_HDD
> +7 10 Fallback_Floppy
> +#7 3 ROM
> +
> +checksums
> +
> +checksum 392 1007 1008
> +
> +
> Index: mainboard/jetway/j7f2we/Makefile
> ===================================================================
> --- mainboard/jetway/j7f2we/Makefile (revision 0)
> +++ mainboard/jetway/j7f2we/Makefile (revision 0)
> @@ -0,0 +1,50 @@
> +##
> +## This file is part of the LinuxBIOS project.
> +##
> +## Copyright (C) 2006-2007 coresystems GmbH
> +## (Written by Stefan Reinauer <[EMAIL PROTECTED]> for coresystems GmbH)
> +##
> +## This program is free software; you can redistribute it and/or modify
> +## it under the terms of the GNU General Public License as published by
> +## the Free Software Foundation; either version 2 of the License, or
> +## (at your option) any later version.
> +##
> +## This program is distributed in the hope that it will be useful,
> +## but WITHOUT ANY WARRANTY; without even the implied warranty of
> +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +## GNU General Public License for more details.
> +##
> +## You should have received a copy of the GNU General Public License
> +## along with this program; if not, write to the Free Software
> +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> +##
> +
> +STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
> +
> +STAGE2_MAINBOARD_OBJ =
> +
> +$(obj)/linuxbios.vpd:
> + $(Q)printf " BUILD DUMMY VPD\n"
> + $(Q)dd if=/dev/zero of=$(obj)/linuxbios.vpd bs=256 count=1 $(SILENT)
> +
> +INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \
> + $(obj)/southbridge/via/vt8237r/smbus_initram.o
> +
> +# Next Quest: Make a single rule out of those:
> +$(obj)/mainboard/$(MAINBOARDDIR)/initram.o:
> $(src)/mainboard/$(MAINBOARDDIR)/initram.c
> + $(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c $< -o $@
> +$(obj)/northbridge/via/cn700/raminit.o:
> $(src)/northbridge/via/cn700/raminit.c
> + $(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c $< -o $@
> +$(obj)/southbridge/via/vt8237r/smbus_initram.o:
> $(src)/southbridge/via/vt8237r/smbus_initram.c
> + $(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c $< -o $@
> +
> +$(obj)/linuxbios.initram $(obj)/linuxbios.initram.map: $(obj)/stage0.init
> $(obj)/stage0-prefixed.o $(INITRAM_OBJ)
> + $(Q)# initram links against stage0
> + $(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n"
> + $(Q)$(LD) --entry main -N -R $(obj)/stage0-prefixed.o \
> + $(INITRAM_OBJ) -o $(obj)/linuxbios.initram.o
> + $(Q)printf " OBJCOPY $(subst $(shell pwd)/,,$(@))\n"
> + $(Q)$(OBJCOPY) -O binary $(obj)/linuxbios.initram.o \
> + $(obj)/linuxbios.initram
> + $(Q)printf " NM $(subst $(shell pwd)/,,$(@))\n"
> + $(Q)$(NM) $(obj)/linuxbios.initram.o | sort -u >
> $(obj)/linuxbios.initram.map
> Index: arch/x86/stage1.c
> ===================================================================
> --- arch/x86/stage1.c (revision 507)
> +++ arch/x86/stage1.c (working copy)
> @@ -51,7 +51,52 @@
> post_code(0xf2);
> }
>
> +/* From v2, amd k8 car. Might work, might need some research */
> +inline __attribute__((always_inline)) void disable_car(void)
> +{
>
> + __asm__ volatile (
> +
> + /* We don't need cache as ram for now on */
> + /* disable cache */
> + "movl %cr0, %eax\n\t"
> + "orl $(0x1<<30),%eax\n\t"
> + "movl %eax, %cr0\n\t"
> +
> + /* clear sth */
> + "movl $0x269, %ecx\n\t" /* fix4k_c8000*/
> + "xorl %edx, %edx\n\t"
> + "xorl %eax, %eax\n\t"
> + "wrmsr\n\t"
> +#if DCACHE_RAM_SIZE > 0x8000
> + "movl $0x268, %ecx\n\t" /* fix4k_c0000*/
> + "wrmsr\n\t"
> +#endif
> +
> + /* disable fixed mtrr from now on, it will be enabled by
> linuxbios_ram again*/
> + "movl $0xC0010010, %ecx\n\t"
> +// "movl $SYSCFG_MSR, %ecx\n\t"
> + "rdmsr\n\t"
> + "andl $(~(3<<18)), %eax\n\t"
> +// "andl $(~(SYSCFG_MSR_MtrrFixDramModEn |
> SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t"
> + "wrmsr\n\t"
> +
> + /* Set the default memory type and disable fixed and enable variable
> MTRRs */
> + "movl $0x2ff, %ecx\n\t"
> +// "movl $MTRRdefType_MSR, %ecx\n\t"
> + "xorl %edx, %edx\n\t"
> + /* Enable Variable and Disable Fixed MTRRs */
> + "movl $0x00000800, %eax\n\t"
> + "wrmsr\n\t"
> +
> + /* enable cache */
> + "movl %cr0, %eax\n\t"
> + "andl $0x9fffffff,%eax\n\t"
> + "movl %eax, %cr0\n\t"
> +
> + );
> +}
> +
Can you explain? Why it this here at all? You don't seem to call it. Why
is it in stage1.c and not stage0_i586.S? Does it work? Does it work
for any x86 system of only K8?
Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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