Hello,
Following patch (fidvid.patch) adds support for FID/VID changes messages. Upon
incoming SMAF message from CPU (C3 or FID/VID change), the SB will assert SLP#
which is connected to LDTSTOP_L on K8 CPUs. Question is for how long. Imho for
100us. Which is more than plenty (2us required) I will try to justify this once
I know what bios to set in SB.
Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]>
Second patch just gives an example what needs to be in DSDT to make it actually
work. Usually this part is stored in secondary DSDT table (SSDT), which is build
in runtime in BIOS. The values are computed for the CPU used in the system and
cannon be static. I dont know how to do the computations yet.
Rudolf
Index: southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- southbridge/via/vt8237r/vt8237r_lpc.c (revision 2953)
+++ southbridge/via/vt8237r/vt8237r_lpc.c (working copy)
@@ -222,6 +222,13 @@
/* SCI is generated for RTC/pwrBtn/slpBtn. */
outw(0x001, VT8237R_ACPI_IO_BASE + 0x04);
+
+ /* FIXME: Intel needs more bit set for C2/C3 */
+
+ /* Allow SLP# signal to assert LDTSTOP_L
+ * Will work for C3 and for FID/VID change
+ */
+ outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
}
static void vt8237r_init(struct device *dev)
Index: mainboard/asus/a8v-e_se/cache_as_ram_auto.c
===================================================================
--- mainboard/asus/a8v-e_se/cache_as_ram_auto.c (revision 2953)
+++ mainboard/asus/a8v-e_se/cache_as_ram_auto.c (working copy)
@@ -309,6 +309,12 @@
#endif
init_timer();
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
+
+#if K8_SET_FIDVID == 1
+ enable_fid_change();
+ init_fidvid_bsp(bsp_apicid);
+#endif
+
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
Index: mainboard/asus/a8v-e_se/dsdt.asl
===================================================================
--- mainboard/asus/a8v-e_se/dsdt.asl (revision 2953)
+++ mainboard/asus/a8v-e_se/dsdt.asl (working copy)
@@ -35,6 +35,141 @@
{
Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {}
Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {}
+
+ Scope (\_PR.CPU0)
+ {
+ Name (_PCT, Package (0x02)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ },
+
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ }
+ })
+ Name (_PSS, Package (0x04)
+ {
+ Package (0x06)
+ {
+ 0x00000898,
+ 0x0001ADB0,
+ 0x00000064,
+ 0x00000009,
+ 0xE0202A0E,
+ 0x0000020E
+ },
+
+ Package (0x06)
+ {
+ 0x000007D0,
+ 0x00019C80,
+ 0x00000064,
+ 0x00000009,
+ 0xE0202A8C,
+ 0x0000028C
+ },
+
+ Package (0x06)
+ {
+ 0x00000708,
+ 0x00015C0C,
+ 0x00000064,
+ 0x00000009,
+ 0xE0202B0A,
+ 0x0000030A
+ },
+
+ Package (0x06)
+ {
+ 0x000003E8,
+ 0x0000BF68,
+ 0x00000064,
+ 0x00000009,
+ 0xE0202C82,
+ 0x00000482
+ }
+ })
+ Name (_PPC, 0x00)
+ }
+
+ Scope (\_PR.CPU1)
+ {
+ Name (_PCT, Package (0x02)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ },
+
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ }
+ })
+ Name (_PSS, Package (0x04)
+ {
+ Package (0x06)
+ {
+ 0x00000898,
+ 0x0001ADB0,
+ 0x00000064,
+ 0x00000009,
+ 0xE0202A0E,
+ 0x0000020E
+ },
+
+ Package (0x06)
+ {
+ 0x000007D0,
+ 0x00019C80,
+ 0x00000064,
+ 0x00000009,
+ 0xE0202A8C,
+ 0x0000028C
+ },
+
+ Package (0x06)
+ {
+ 0x00000708,
+ 0x00015C0C,
+ 0x00000064,
+ 0x00000009,
+ 0xE0202B0A,
+ 0x0000030A
+ },
+
+ Package (0x06)
+ {
+ 0x000003E8,
+ 0x0000BF68,
+ 0x00000064,
+ 0x00000009,
+ 0xE0202C82,
+ 0x00000482
+ }
+ })
+ Name (_PPC, 0x00)
+ }
+
}
/* For now only define 2 power states:
--
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